This thesis explores the vast field of physically implementing parallel-computing algorithms. In this research, we introduce a series of new circuit architectures and new technology applications, which implement multi-dimensional functions that are at the heart of many parallel signal processing systems, e.g., neural and Hamming networks, vector quantizers, and median filters. The functions are realized using low-cost, low-power, high-density technologies (CMOS and CCD), fully compatible with current industrial processes. The systems are either analog or hybrid, allowing lower time and/or storage complexities in many types of applications when compared to fully digital systems. Special emphasis is placed on circuit modeling, with the purpose of thoroughly understanding the potentialities - and limitations - of each alternative. The models are verified experimentally on most occasions. As a consequence, the results presented in this dissertation are expected not only to provide new technological alternatives, but also new means of evaluating the technologies themselves.
Chapter 1 presents an introductory discussion on parallel systems. It has three main purposes. One is to describe some of the parallel functions whose implementations we are interested in. Another is to present a graphical discussion on how certain multidimensional systems work, which is probably the best way of describing - and appreciating - systems of this kind. And finally to describe basic guidelines concerning this research.
Chapter 2 discusses a function that is inherent to most analog parallel processors, the winner-take-all function. The reason for it to be developed first is that this function is part of many other function realizations. A global discussion is presented, which provides an overview on the potentialities of most implementations available in CMOS technology, followed by high-resolution alternatives. The use of this function to implement other functions and systems is also illustrated.
Chapter 3 presents a detailed discussion on charge-coupled device (CCD) technology and its applications to parallel signal processing systems. This technology, compatible with conventional double-poly CMOS, is of interest due to its low power consumption and very high integration density, allowing the construction of very efficient vector-matrix multipliers and Hamming networks. To overcome its main limitation (i.e., charge-transfer inefficiency), a locally-controlled architecture is introduced. Several chips and extensive measurements are shown, with the purpose of concretely evaluating the performance of this technology when performing signal processing tasks.
Finally, Chapter 4 describes further research on CMOS cells that compute distance-based functions. These circuits allow the construction of LMS and other distance-based parallel processors, and provide additional valuable means of further examining the use of MOS technology for analog computation. Once again experimental results are presented, and the systems are illustrated through vector quantizers, Hamming networks, vector multipliers, and median filters. This chapter also provides further applications of the winner-take-all function to the construction of more complex functions
