The application of Field Programmable Gate Array (FPGA) in the development of power electronics circuits control scheme has drawn much attention lately due to its shorter design cycle, lower cost and higher density. This paper presents an FPGA-based gate signal generator for a multilevel inverter employing an online optimal PWM switching strategy to control its output voltage. FPGA is

chosen for the hardware implementation of the switching strategy mainly due to its high computation speed that can

ensure the accuracy of the instants that gating signals are

generated. The gate signal generator has been realized by an FPGA (FLEXlOKZO) from Altera. The design and development of the FPGA based gate signal generator is

described in detail. Results from the timing simulation using MAX+PLUSII software are given and verified by the results obtained from the FLEXlOK2O output

Azli, N. Ahmad

Salim, F.

English

Universiti Teknologi Malaysia Institutional Repository

Development of an FPGA-Based Gate Signal Generator for a Multilevel Inverter F. Salim', N. Ahmad Azli' I Electrical Engineering Department, Program Pengajian Diploma, Universiti Teknologi Malaysia, Malaysia. 'Energy Conversion Department, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Malaysia. Abstract-The application of Field Programmable Gate Array (FPGA) in the development of power electronics circuits control scheme has drawn much attention lately due to its shorter design cycle, lower cost and higher density. This paper presents an FPGA-based gate signal generator for a multilevel inverter employing an online optimal PWM switching strategy to control its output voltage. FPGA is chosen for the hardware implementation of the switching strategy mainly due to its high computation speed that can ensure the accuracy of the instants that gating signals are generated. The gate signal generator has been realized by an FPGA (FLEXlOKZO) from Altera. The design and development of the FPGA based gate signal generator is described in detail. Results from the timing simulation using MAX+PLUSII software are given and verified by the results obtained from the FLEXlOK2O output. Keywords-FPGA, optimal PWM, multilevel inverter. I. INTRODUCTION The first concept of multilevel inverter studies began at the end of the seventies, but no practical use of it was made then [I]. In 198 1, the Neutral Point Clamped (NPC) inverter was introduced [2]. In the early nineties, the interest in the multilevel structure was renewed with the emergence of various circuit topologies and modulation strategies. There are three main types of multilevel inverters, which can be classified as Diode Clamped Multilevel Inverter (DCMI), Imbricated Cells Multilevel Inverter (ICMI) and Modular Structured Multilevel Inverter (MSMI). A work reported earlier [3][4][6] on the development of an online optimal PWM switching strategy for a 5-level MSMI employed a dSPACE DS1101 controller board to fulfill the tasks of calculating in real time the optimal PWM switching angles as well as generate the gating signals for each of the MSMI power devices. The DS1102 controller board is based on the Texas Instruments TMS320C3 1 floating-point DSP, which builds the main processing unit, providing fast instruction cycle time for numeric intensive algorithm. However, using the DS I 102 controller board, the tasks mention above can only be accomplished within the sampling time of 100psec that corresponds to a 1.8" resolution for the switching angles. A large sampling interval holds the effect of deviating the timings of the gating signals generated by the DSP from the actual optimal PWM switching angles calculated by it using derived functions that will be explained later. This paper proposes the incorporation of an FPGA-based gate signal generator with the DSP to relief the later from time consuming computation task of the gating signals generation. Thus, the overall sampling time to generate the gating signals for the MSMI power devices can be reduced further for better timing precision. Description on the MSMI circuit topology is given in the following section. This is followed by the details on the MSMI control operation system and the development of the FPGA-based gate signal generator. The results obtained from the timing simulation and the actual FPGA output is presented for comparison purposes. Finally, a conclusion is made based on the work 1 hat has been done. 11. THE MSMI In general, an MSMI consists of (nl- 1)/2 or h number of single-phase H-bridge inverters referred to as MSMI modules, that are connected in series to generate an nl level output phase voltage. A single-phase structure of a single-phase MSMI is shown in Fig. 1. The MSMI output phase voltage is equal to the summation of the output voltages of the respective modules that is, v, = V,I f v,1 -k . ....... Vmh (1) Module 2 I ,.t" I ModJe h Fig. I .  Structure ofa singlc-phase nl-lcvcl MSMI 402 Each MSMI module has its own DC source (VDC) and consists of four power devices designated as SI,, S?,, S,, and S4, where r = 1,2, ... h. Each MSMI module can generate a three-level output namely + VDc, 0 and - V D ~ .  This is made possible by connecting the DC source sequentially to the AC side via the four power devices. As an example, for an output phase voltage consisting of 5 levels, which are + 2 V ~ c ,  + V D ~ ,  0,  -VDC and - 2 v D C ,  the number of modules required in the MSMI is two. The MSMIs are known to eliminate the excessively large number of clamping diodes required by the DCMIs and capacitors required by the ICMIs. Its circuit configuration is simple and modular where by each of its module is identical and incorporate both input and output circuitry [ 5 ] .  In addition it also requires the least number of components compared to the other types of multilevel inverter. These features provide the flexibility in extending the MSMI to higher number of levels without undue increase in circuit complexity simplifies fault finding and repair as well as facilitates packaging. Ycs 111. THE MSMI CONTROL OPERATION No A .  The DSI 102 Contsolles Boasd From the voltage signal sent to represent a particular apl value, the switching angles are calculated by the DSI 102 controller board using the functions that represent each of the switching angles solution trajectories of the optimal PWM switching strategy. The functions are in the form of [6], Fk=a,+al [(apI-m)]+a2 [(apl-m)'] + . . . .. a,[(apl -m)Y] ( 2 )  where, k = 1 and 2,  apl-m is the amplitude of the fundamental of each MSMI module's output in per unit value. Examples of the coefficient values used are as given by Table 1. The functions are accessed based on the multilevel control design [4][6] of the 5-level MSMI, which depends on the apl values. Fig. 3 generally illustrates how the multilevel control design is implemented on the DSP and the way the functions are being accessed to calculate the optimal PWM switching angles. DSI 102 Controller . Board (TMS320C3 1) Fig. 3. Iinplcincntntion ofthc niultilcvcl control dcsign on the DSP Fig. 2.  Block Diagram ofthc MSMI control opcrntion systcin B. The FPGA 403 The limitations in the number of input-output pins on the DS 1 I02 controller board makes it impossible to feed the switching angles values directly to the FPGA. Thus, the approach taken in this case is to group the switching angles calculated online by the DSP depending on the apl value into categories known as case number. Each case number relates to certain timing values of the gate signal, which are pre-calculated and stored in the FPGA. In other words, the FPGA generates the gate signals based on the case number received from the controller board. The case number can be determined by referring to all the count values for each apl value. In this work, the value of count is calculated for ap f  in steps of 0.02 and 25 cases have been determined. The fixed value of count for each MSMI module is also stored in the FPGA. The count value for the power devices in module 1 of the MSMI is called ncoitnter while for power devices in module 2 the count value is known as counter. For example, the count value for module 1 of the MSMI can be calculated using (2) where OL is the switching angle. After all values of the ncoitnter and counter for each value of up/ have been calculated, the case number is determined. This number represents different sets of count values. Based on the relevant values of ncoitnter and counter identified by the FPGA for each cuse number, the gate signals are generated. The design based on this approach is described in schematic and Very High Speed Integated Circuit Hardware Description Language (VHDL). It is then verified via both functional and timing simulations using the MAX+PLUSIT software. Fig. 4 shows the top-level module for the gate signal generator. Module counter58us and ncoiinter58us represent the timing values while module gensig58us serves to generate the gate signals. The design is then downloaded to the FPGA, in this case the FLEXIOK20, which continues to operate as long as it is power up. IV. RESULTS AND ANALYSIS With the introduction of the FPGA based gate signal generator, the DSP function has been limited to only calculating the switching angles. The sampling time to generate the gate signals ha:; been reduced to 58 psec and the switching angles resolution is 1.044". This value represents the sampling time achievable by the DSP in handling the tasks of calculating the optimal PWM switching angles and detennining the case number. The FPGA is actually constrained to this sampling time in order to generate the gate signals. Fig. 5 and Fig. 6 show the simulation results obtained from the gate signal generator for up /  = 0.4 and up/  = 0.7. Fig. 7and Fig. 8 show the results obtained from the FLEXIOKZO output for u p /  = 0.4 and apl = 0.7 that represents the actual gate signals for the MSMI power devices. Only four signals are shown, as the other four signals are merely the complement of these four signals as can be depicted from the simulation results. b:: ~ : = = i r ~ r r + l  Fig 5 Simulation rcsults for ap l  = 0 4 Kame 7Fig. 6. Simulation results for a p l  = 0.7 Fig. 4. Schematic diagram of the gate signal generator 404 g2 1 g12 5.00 ms/d!v  Fig. 7. Gate s iga l s  generated by the FLEXIOK2O for up1 = 0.4 g12 g22 25 000 m; 0.000 s 25.000 ms 5.00 m s l d i v  real time Fig. 8. Gate signals generated by the FLEXIOK2O for up1 = 0.7 The gate signals generated by the FLEXIOK20 show good agreement to those obtained from the functional and timing simulations using the MAX+PLUSII software. Based on a hybrid PWM switching arrangement [6], any pair of the four power devices in each MSMI module is pulsewidth-modulated at a higher frequency while the other pair is commutated at a low output voltage fundamental frequency. In this work, SI ,  and of module 1 and S12 and Sj2 of module 2 are assigned to switch at the MSMI output voltage fundamental frequency of 50 Hz. On the other hand, SZI and SJI of module 1 and SZ2 and Sd2 of module 2 are assibmed to switch at the higher switching frequency. These features can be depicted from Fig. 5 to Fig. 8. v. CONCLUSION on a DSl102 controller board. The design and implementation of the gate signal generator using the MAX+PLUSII software and Altera’s FLEX 10K20 have been described. With the introduction of the FPGA based gate signal generator, the DSP’s task has been reduced thus reducing the sampling time required in calculating the optimal PWM switching angles and determining the relevant case number as the input to the FPGA. REFERENCES [ I  J S .  M. Tcnconi, M. Carpita, C. Bacigalupo. and R. Cali, .‘ Multilcvcl voltage source convcrtes for medium voltage adjustable spccd drives.” in Proc. oftlie IEEE Internutionul Sytnpositim on Itidtistrial Electronics ISIE ‘YS. pp. 9 1-98. [2] A. Nabac, I, Takahashi and H. Akagy. “A neutral point clamped PWM invcrtcr.” IEEE Transactions on lndiistry Applications, vol. 17, no. 5, pp. 518-523, 1981. [3] N. A. Azli and A. H. M. Yatim. “Modular structured multilevel inverter (MSMI) for hizh powcr AC powcr supply application”, in Proc. of’ the IEEE Interntrtional Syniposiirni on Indtistriol Electronics ISIE’ 01, Pusan, Korca, pp. [4] N. A. Azli. and A. H. M. Yatim, “Optimal pulsewidth modulation (PWM) online control of a modular structured multilevel inverter (MSMI)”, presented at the 4’” IEEE lntcrnational Confcrcncc on Power Electronics and Drive Systems, Bali. Indonesia, 2001, [5] C. Newton and M. Sumncr, “Multi-lcvcl Convcrtors a Real Solution to Mcdiumihigh-voltage Drivcs‘?.” Power Engi~ireringJotirnirI.. pp. 21-26, 1998. [6] N. A. AA,,  “Online optimal pulscwidth modulation (PWM) for a modular stnicturcd multilcvcl inverter.” .Ph.D. dissertation, Elect. Eng. Program, Univ. Tcknologi Malaysia. Johor, Malaysia, 2002. 728-733.. This paper presents the application of an FPGA in developing a gate signal generator for an MSMI based on the optimal PWM switching angles calculated by a DSP 405 

Development of an FPGA-based gate signal generator for a multilevel inverter

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Development of an FPGA-based gate signal generator for a multilevel inverter

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