An updated edition of the classic book on computer architecture by J. L. Hennessy and D. A. Patterson.\nAuthors show their high level standards for technological ideas, writing style, and teaching methodologies, all in one book. In fact, they maintain their quality since the first edition of this book. As authors explain, one of the main reasons for the fourth edition of the book is the focus on parallel architectures for high performance, more specifically: multiple processors or processors cores per chip designs

Tinetti, Fernando Gustavo

Journal of Computer Science and Technology

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Book ReviewComputer Architecture: A Quantitative ApproachJ. L. Hennessy, D. A. PattersonMorgan Kaufman, 4th Edition, 2007ISBN 0-12-370490-1An updated edition of the classic book on computer architecture by J. L. Hennessy and D. A. Patterson. Authors  show  their  high  level  standards  for  technological  ideas,  writing  style,  and  teaching methodologies, all in one book. In fact, they maintain their quality since the first edition of this book. As authors  explain,  one of  the main reasons for  the fourth edition of  the  book is  the  focus on parallel architectures for high performance, more specifically: multiple processors or processors cores per chip designs.Distribution of material in chapters is as follows:• Chapter  1:  Fundamentals  of  Computer  Design.  This  chapter  introduce  and  define  terms  used throughout the book. Important issues such as power consumption and cost are included, along with performance measuring.• Chapter 2:  Instruction-Level Parallelism and Its Exploitation. A complete description of advantages, problems and solutions to ILP by pipelining techniques. Most of the concepts are explained by using MIPS  and  some  possible  implementations.  Authors  explicitly  refer  to  Appendix  A  for  a  more detailed description of MIPS pipelining. Also, in the beginning of Appendix A authors refer to a more basic text on computer architecture and design for a more detailed description of instruction pipelining in general. These references give an idea of the advanced level of coverage given to ILP in the second chapter of the book.• Chapter 3: Limits on Instruction Level Parallelism. This chapter explains strong studies to ILP limits, along  with  the  main  ideas  underlying  thread-level  parallelism.  Also,  advanced  concepts  of speculative instruction execution are presented, comparing hardware and software approaches.• Chapter 4: Multiprocessors and Thread-Level Parallelism. Multiprocessors are presented as a natural evolution of processing architecture due to limits in single processor performance. The introduction of the chapter begins with a simple but useful taxonomy of processing hardware. Other important concepts such as symmetric multiprocessing with shared memory and distributed shared memory are also discussed in this chapter. An interesting complete example is also included after discussing general concepts.• Chapter 5: Memory Hierarchy Design. Memory plays a crucial role in processing performance, and most  of  the  involved  issues  are  included  in  this  chapter.  In  fact,  the  previous  chapter  can  be considered  a  thorough  introduction  to  the  memory  hierarchy  of  computing  systems.  Again,  a complete  and real  example  is  presented,  which shows most  of  the  design decisions  made on a specific architecture produced for the market.• Chapter 6: Storage Systems. Disks and general I/O design issues are presented in this chapter. As in the  beginning  of  the  book,  specific  definitions  for  performance  measuring  and  benchmark  are presented specifically for the I/O subsystem.Clearly, there are chapters in two  general classes: hardware for processing, and memory and storage harware, the latter including I/O because of the relationship of disks with the computers' I/O subsystem. Also, the printed book includes three long appendices:• Appendix A. Pipelining: Basic and Intermediate Concepts. • Appendix B. Instruction Set Principles and Examples.• Appendix C. Review of Memory Hierarchy.The book has a companion CD, with eight Appendices:• Appendix D. Embedded Systems. JCS&T Vol. 8 No. 3                                                                                                                              October 2008168• Appendix E. Interconnection Networks.• Appendix F. Vector Processors. • Appendix G. Hardware and Software for VLIW and EPIC.• Appendix H. Large Scale Multiprocessors and Scientific Applications.• Appendix I. Computer Arithmetic.• Appendix J. Survey of Instruction Set Architectures.• Appendix K. Historical Perspectives and References. Every  appendix  can  be  considered  a  thorough  description  and  discussion  of  a  specific  computer architecture detail. Authors have been careful in including extensive and technical information on all of the appendices, many of them being complete and useful computing architecture reviews. Finally, the book also has an online appendix: Appendix L. Solutions to Case Study Exercises, which is useful mainly for teachers and students. This book is one of the main sources for advanced computer architecture courses at university grade and at post grade levels.       Fernando G. Tinetti                  III-LIDI, Fac. Informática, UNLP             Inv. Asistente Comisión Inv. Científicas                    de la Provincia de Buenos Aires  fernando@info.unlp.edu.arJCS&T Vol. 8 No. 3                                                                                                                              October 2008169

Computer Architecture: A Quantitative Approach J. L. Hennessy, D. A. Patterson Morgan Kaufman, 4th Edition, 2007

An updated edition of the classic book on computer architecture by J. L. Hennessy and D. A. Patterson.
Authors show their high level standards for technological ideas, writing style, and teaching methodologies, all in one book. In fact, they maintain their quality since the first edition of this book. As authors explain, one of the main reasons for the fourth edition of the book is the focus on parallel architectures for high performance, more specifically: multiple processors or processors cores per chip designs.Facultad de Informátic

El Servicio de Difusión de la Creación Intelectual

Book Review
Computer Architecture: A Quantitative Approach
J. L. Hennessy, D. A. Patterson
Morgan Kaufman, 4th Edition, 2007
ISBN 0-12-370490-1
An updated edition of the classic book on computer architecture by J. L. Hennessy and D. A. Patterson. 
Authors  show  their  high  level  standards  for  technological  ideas,  writing  style,  and  teaching 
methodologies, all in one book. In fact, they maintain their quality since the first edition of this book. As 
authors  explain,  one of  the main reasons for  the fourth edition of  the  book is  the  focus on parallel 
architectures for high performance, more specifically: multiple processors or processors cores per chip 
designs.
Distribution of material in chapters is as follows:
• Chapter  1:  Fundamentals  of  Computer  Design.  This  chapter  introduce  and  define  terms  used 
throughout the book. Important issues such as power consumption and cost are included, along with 
performance measuring.
• Chapter 2:  Instruction-Level Parallelism and Its Exploitation. A complete description of advantages, 
problems and solutions to ILP by pipelining techniques. Most of the concepts are explained by using 
MIPS  and  some  possible  implementations.  Authors  explicitly  refer  to  Appendix  A  for  a  more 
detailed description of MIPS pipelining. Also, in the beginning of Appendix A authors refer to a 
more basic text on computer architecture and design for a more detailed description of instruction 
pipelining in general. These references give an idea of the advanced level of coverage given to ILP 
in the second chapter of the book.
• Chapter 3: Limits on Instruction Level Parallelism. This chapter explains strong studies to ILP limits, 
along  with  the  main  ideas  underlying  thread-level  parallelism.  Also,  advanced  concepts  of 
speculative instruction execution are presented, comparing hardware and software approaches.
• Chapter 4: Multiprocessors and Thread-Level Parallelism. Multiprocessors are presented as a natural 
evolution of processing architecture due to limits in single processor performance. The introduction 
of the chapter begins with a simple but useful taxonomy of processing hardware. Other important 
concepts such as symmetric multiprocessing with shared memory and distributed shared memory are 
also discussed in this chapter. An interesting complete example is also included after discussing 
general concepts.
• Chapter 5: Memory Hierarchy Design. Memory plays a crucial role in processing performance, and 
most  of  the  involved  issues  are  included  in  this  chapter.  In  fact,  the  previous  chapter  can  be 
considered  a  thorough  introduction  to  the  memory  hierarchy  of  computing  systems.  Again,  a 
complete  and real  example  is  presented,  which shows most  of  the  design decisions  made on a 
specific architecture produced for the market.
• Chapter 6: Storage Systems. Disks and general I/O design issues are presented in this chapter. As in 
the  beginning  of  the  book,  specific  definitions  for  performance  measuring  and  benchmark  are 
presented specifically for the I/O subsystem.
Clearly, there are chapters in two  general classes: hardware for processing, and memory and storage 
harware, the latter including I/O because of the relationship of disks with the computers' I/O subsystem. 
Also, the printed book includes three long appendices:
• Appendix A. Pipelining: Basic and Intermediate Concepts. 
• Appendix B. Instruction Set Principles and Examples.
• Appendix C. Review of Memory Hierarchy.
The book has a companion CD, with eight Appendices:
• Appendix D. Embedded Systems. 
JCS&T Vol. 8 No. 3                                                                                                                              October 2008
168
• Appendix E. Interconnection Networks.
• Appendix F. Vector Processors. 
• Appendix G. Hardware and Software for VLIW and EPIC.
• Appendix H. Large Scale Multiprocessors and Scientific Applications.
• Appendix I. Computer Arithmetic.
• Appendix J. Survey of Instruction Set Architectures.
• Appendix K. Historical Perspectives and References. 
Every  appendix  can  be  considered  a  thorough  description  and  discussion  of  a  specific  computer 
architecture detail. Authors have been careful in including extensive and technical information on all of 
the appendices, many of them being complete and useful computing architecture reviews. 
Finally, the book also has an online appendix: Appendix L. Solutions to Case Study Exercises, which is 
useful mainly for teachers and students. 
This book is one of the main sources for advanced computer architecture courses at university grade and 
at post grade levels. 
      Fernando G. Tinetti
                  III-LIDI, Fac. Informática, UNLP
             Inv. Asistente Comisión Inv. Científicas
                    de la Provincia de Buenos Aires
  fernando@info.unlp.edu.ar
JCS&T Vol. 8 No. 3                                                                                                                              October 2008
169


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Computer Architecture: A Quantitative Approach J. L. Hennessy, D. A. Patterson Morgan Kaufman, 4th Edition, 2007

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