The continuous scaling-down process of the channel length over the last four decades is reaching its limits in terms of gate oxide thickness, short channel effects and power consumptions, all the above issues driving increased leakage currents. The dual gate SOI CMOSFET devices are expected to replace the bulk CMOSFET transistors for a better control of the entire device electrostatics. In this context, the current thesis proposes an one-dimensional analytical modeling of a novel symmetric Double-Gate SOI CMOSFET transistor, covering the dc and ac analyses, as well as its potential nano-electronics and RF MEMS applications. Our methodology offers a good characterization of the device in all regions of operation with the only assumptions of the light doping of the substrate and constant electron mobility. The silicon electrostatic potentials, inversion charge, electrical current drain and the small-signal parameters in terms of transconductance and output conductance are calculated for a silicon thickness of 20 nm, so that the volume inversion feature to be analytically proved, for 1 V voltage supply. A major contribution of the work is also, the AC analysis of an un-doped symmetric SOI MOSFET device, starting from the derivation of the small-signal circuit, continuing with the evaluation of terminal charges and capacitances and ending with the calculation of the RF figures of merits such as the cut-off frequency and the maximum frequency of oscillation. In addition, the thesis introduces the idea of the asymmetry behavior of the symmetric DG SOI MOSFET as a function of the applied channel voltage. Further, the work emphasizes the specific challenges of the analytical modeling for asymmetric DG SOI MOSFET devices, where the complexity of the mathematical equations reaches its limits. Our entire analytical model of an un-doped symmetrical DG SOI MOSFET, is implemented in Verilog-A code in order to better support the compact device modeling and make it available for the design of the next generation of circuits. Thus, the new obtained library has been used in "Cadence", the typical design and modeling tool. In accordance with this goal, the operation of a common source amplifier based on the above-developed Verilog A code for the DG SOI MOSFET transistor will be shown. Driven by the present scientific community effort to integrate the RF MEMS vibrating components and the electronic circuits for getting one chip transceiver in the near future, within this thesis we have combined the DG SOI MOSFET circuits with RF MEMS resonators for developing at the virtual level on-chip frequency generating functions. In this case, the thesis presents how the perturbation method can be applied to design a non-linear oscillator comprising of a DG SOI MOSFET device and a RF MEMS resonator used for the positive feedback loop
