A Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select Adder

Abstract

<p>Duet advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Sever a ladder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed modified carry select adder using boot hen coder (BEC) Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family</p