In the literature the influence of the conducting layer, sometimes called a floating gate, upon d.c.-MISFET characteristics is ignored or only treated in a phenomenological way. Our intentions in this paper are to present a study of the consequences of a conducting layer in an exact way by using the MISFET theory described earlier.\ud
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It is found that the d.c.-characteristics are influenced by parasitic capacitances from the conducting layer to source and drain and the charge-voltage relations along the channel of the MIS transistor.\ud
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The theoretical considerations are verified by simulations with Spice 2 and some experimental results and are in agreement with the characteristics already given in the literature referred to

Bergveld, P.

Voorthuyzen, J.A.

English

In the literature the influence of the conducting layer, sometimes called a floating gate, upon d.c.-MISFET characteristics is ignored or only treated in a phenomenological way. Our intentions in this paper are to present a study of the consequences of a conducting layer in an exact way by using the MISFET theory described earlier. It is found that the d.c.-characteristics are influenced by parasitic capacitances from the conducting layer to source and drain and the charge-voltage relations along the channel of the MIS transistor. The theoretical considerations are verified by simulations with Spice 2 and some experimental results and are in agreement with the characteristics already given in the literature referred to

Bergveld, Piet

University of Twente Research Information

Gu38-1101/84 $3.00 + .Gu Persamon Press Ltd. THE CONSEQUENCES OF THE APPLICATION OF A FLOATING GATE ON d.c.-MISFET CHARACTERISTICS J. A. VOORTHWZEN and P. BERGVELD Twente University of Technology, P.O. Box 217, Enschede, The Netherlands (Received 21 July 1983; in revised form 21 September 1983) Abstract-In the literature the influence of the conducting layer, sometimes called a floating gate, upon d.c.-MISFET characteristics is ignored or only treated in a phenomenological way. Our intentions in this paper are to present a study of the consequences of a conducting layer in an exact way by using the MISFET theory described earlier. It is found that the d.c.-characteristics are influenced by parasitic capacitances from the conducting layer to source and drain and the charge-voltage relations along the channel of the MIS transistor. The theoretical considerations are verified by simulations with Spice 2 and some experimental results and are in agreement with the characteristics already given in the literature referred to. NOTATION floating gate-insulator interface floating gate-insulator interface parasitic gate-source capacitance, F parasitic gate-drain capacitance, F oxide capacitance per unit area, F/m2 actual oxide capacitance, F drain current, A channel-length, m density of mobile charge in the channel, C/m* interface charge density, C/m2 interface charge density, C/m2 potential in the channel, V drain-source voltage, V gate-source voltage, V v,-v, V saturation voltage, V threshold voltage, V voltage of the upper layer, V channel-width, m ratio of capacitances, &,,0 W/L, mA/v* ratio of capacitances, drift mobilitv in the channel. mr/Vs fermi-potential difference, V fermi-potential difference, V 1. INTRODUCTION In the past, various types of MISFET structures have been presented in the literature. This paper will be especially restricted to those types of h4ISFETs in which the insulating film consists of two layers, separated by a conducting layer, for instance alumi- num or polysilicon. Examples of this type of device are the MISFET with a floating gate[l], mainly in use as a memory device, the acoustic wave sensing POSFET, in- vestigated by Swartz et aZ.[2], and the ion sensitive field effect transistor, described by Smith et aZ.[3]. A floating gate memory device is characterized by two insulating layers of SiO,, separated by a poly- silicon gate. Memory function is obtained by charge storage on and removal from the floating gate, re- sulting in drain current variations. The POSFET is composed of a conventional MO- SFET and a second insulator of piezoelectric mate- rial, for instance polyvinylidene fluoride (PVF,). This insulator is covered with a second conducting layer that is connected to an external voltage source or ground. Variations of pressure generates electronic charge that is collected on the gate of the transistor. The ion-sensitive field effect transistor, mentioned above, is formed by a layer of for instance silicon- nitride, a floating gate of gold, a very high resistive, ion selective membrane and a solution from which the concentration of a specific ion has to be mea- sured. The gold layer protects the FET structure against diffusion of ions or water. In the literature already mentioned, a functional description of the different devices is given, but the influence of the floating gate on the device character- istics is treated only phenomenologically in less de- tail. This paper reports the results of the study of these devices and the consequences of a floating gate upon the d.c.-transistor characteristics in a more exact way. Although the purposes for which the described types of devices have been developed differ widely, they are conceptually the same. Therefore the configuration as schematically drawn in Fig. 1 can be used in our considerations for all cases. We shall use the coordinate system as given in Fig. 1, with the x-axis along the channel, x equal to zero at the source-channel interface and the y-axis perpen- dicular to the surface. All further descriptions will be given for P-type silicon, n-channel depletion type MOSFETs, as- suming that the insulating layers are homogeneous and plan-parallel to the silicon surface, with the bulk connected to the source. In contradiction to the normal use of a floating gate memory device, we will assume that the insu- lators are perfect and the floating gate is electrically uncharged. We define the conducting layer between the two insulators as the gate with voltage V, with respect to the source. The second conductor that covers the whole configuration is called the upper layer with voltage If,, with respect to the source. 311 312 J. A. V~~RTHUYZEN and P. BERGVELD insulator2 - Insu;ator 1 __ V UP %A vd Fig. I. Cross section of a floating gate structure. Floating gate memory devices are not covered with a conducting upper layer which corresponds to an infinite thickness of the second insulator. By varying the thickness of the second insulator the transistor characteristics will change and thus this thickness can be used as a parameter in calculating these character- istics. It will be clear that in the absence of the floating gate, a conventional MOSFET with a sand- wich insulator results, with its gate identical to the upper layer. 2. MOS TRANSISTOR THEORY The operation of the MOS transistor is well known and has been described extensively in the literature, see for instance[4, 51. In a first order approximation bulk effects are neglected and the density of mobile charge in the channel can be written as: %Xx) = - C,X”(V, - vi--- V(x)) (1) with CuXO the oxide capacitance per unit area, VT the threshold or turn on voltage, V(x) the potential in the channel at location x with respect to the source voltage, and VR the applied gate-source voltage. The drain current 1, can now be written as a function of the applied voltages as follows: Id=p [ (V,- v,v;-; vd’ 1 (2) with p = pW/L.C,,O, V, the drain-source voltage, p the mobility of charge carriers in the channel and W and L the width and length of the channel re- spectively. Note, that for depletion type transistors, as we consider here, V, < 0. The value of Vd for which the mobile charge density in the channel qm(x) equals zero, just at the drain-channel interface can be found by using eqn (1) and realizing that V(L) = V& This value of Vd is called the saturation voltage V,, and is given by: v,, = v, - v,. (3) According to eqn (2) the drain current then reaches its maximum value. For larger values of V, relation (2) will no longer be valid and the drain current is then given by: and thus no longer depends on the drain to source voltage Vk 3. THE FLOATING GATE STRUCTURE We shall now deal in more detail with the floating gate structure, as given in Fig. 2. The parasitic gate-to-source and gate-to-drain capacitances are noted as C,,, and C,, respectively, the capacitance formed by the two conducting layers and insulator 2 as C,,, while the actual oxide capacitance is C,,, with C”, = w.L.c”,=. Parasitic capacitances are always present in the practical cases as mentioned in the introduction. The sensitivity of the POSFET configuration was strongly influenced by the presence of a very large gate-to- source capacitance. Even in conventional MOSFET fabrication these capacitances are inevitable. To simplify further descriptions we now distinguish between the situation in which parasitic gate capaci- tances are much larger than the actual oxide capaci- tance C,,, and the situation in which parasitic capac- itances are absent. (a) A jioating gate with large parasitic capacitances If the parasitic capacitances are much larger than the actual oxide capacitance C,,, we can ignore the influence of the latter without making a large error. By applying a voltage VuP to the upper plate with respect to the source and realizing the floating gate to be electrically uncharged, the gate-to-source voltage V, is totally determined by the applied voltages and the capacitances C,,, C,, and C,,. We can write: v = C,Jli + G,V”, p c,, + c,, + Cup’ (5) If the upper plate voltage is equal to zero, we can write the drain current Id as a function of the drain-to-source voltage, by using relations (2) and (5): Id=/3 (uvd- VT)V,--; v ,2 1 (6) V UP vd Fig. 2. Capacitances in a floating gate structure Application of a floating gate on d.c.-MISFET characteristics 313 with c( = C,,/(C,, + C,, + CUP), always positive and smaller than unity. The value of V,, for which the channel is pinched off, just at the drain-channel interface, can be found in a way, analogous to considerations for con- ventional MOSFET theory as given in eqns (l-4), and we then obtain: v,*, = - V&l - LX). (7) In normal saturated MOSFET operation the drain current is independent of drain-to-source voltage variations, see eqn (4), but in the case of a floating gate with large parasitic capacitances the gate-to- source voltage always depends on Vd and for the saturated drain current we have to write: zd=p [ (aV,- vp:,-; v$ I . (8) For n-channel depletion type transistors the thresh- old voltage will be negative, and thus Vzt will always be positive. The J,-V, characteristics for VuP equal to zero and several values of CL are calculated and given in Fig. 3, with VT= -3 V, and fi = 1 mA/V’. The characteristics are strongly dependent on the value of CL If GI equals zero, normal MOSFET char- acteristics with V, = 0 result, while for a = 0.5 a linear characteristic is obtained. Note that in this case the drain current is a linear function of V, for all values, although the device is operating in the satur- ated region if Vd > Vzt = - 2 V,. (b) A jfoating gate without parasitic capacitances In this case we assume no parasitic capacitances are present. Therefore we can no longer neglect the influence of the actual oxide capacitance C,,. If we assume C,, to be equally divided into a gate-to-source and a gate-to-drain capacitance, then no essential differences with the previously discussed situation can be expected. This case would behave as the curve with c[ = 0.5 in Fig. 3. a=O.9 0.7 0 2 4 6 - “d Fig. 3. Calculated lsVd characteristics if parasitic capaci- tances are dominating, with a as a parameter, Vup = 0 V, V,=-3Vandj3=lmA/V2. In the following consideration however we shall explain that such a symmetrical division introduces unacceptable errors for increasing values of the drain- source voltage V+ The expression for the charge density per unit area qg,, at the floating gate-insulator 1 interface can easily be derived from the MOSFET theory already known: qgl = COXOIVP - 4,s - 2&- V(x)1 (9) with 4, the difference in contact potential between the metal of the floating gate and the doped silicon, and & the difference in fermi potential between the doped bulk silicon and intrinsic silicon. At the floating gate-insulator 2 interface the charge density qg2 per unit area equals: q&-z = C”,YV, - V”,l (10) with C UPo = CUP/( W.L.), assuming the upper layer and the floating gate to be of equal size and shape. In the unsaturated mode the potential V(x) in the channel can be written as a function of Vd, V, and VT, by substituting in eqn (2) V(x) for Vd and x for L: V(x)= v;-v:*- v@S [ 112 (11) where = V, V, Although densities at floating gate insulator can be we the gate be and thus: with A, A2 the gate-insulator 1 2 surface By combining eqns we obtain an expression for gate-to-source voltage, be simplified to relation similar to eqn If, = &,,, + 24, + y . Vu,, + VA2 Vd - 3 V;)/(3 Vd - 6 V;) l+Y (13) with y = CUP/C,, = CUPO/COXu. By rearranging relation (13) a second-order expres- sion for Vg is obtained, and thus the IsVd character- istics with y as a parameter can be calculated. Results for V,,=O, VT= -3V, &,+2&= -0.4V and B = 1 mA/V2 are given in Fig. 4. Zero thickness of the second insulator results in a conventional MOSFET and relation (13) is reduced to V, = Vu,, because y becomes infinite. In the satur- ated mode of operation the potential V(x) along the channel no longer depends on V, and thus V, as well as the drain current Id become constant. It is not our purpose to discuss the a.c.-characteristics of the floating gate structure, but 314 J. A. VCORTHUYZEN and P. BERGVELD I I I I 0 1 2 3 - vd [Volt] 4 Fig. 4. Calculated IaV,, characteristics if parasitic capaci- tances are absent, with y as a parameter, Vup = 0, VT=-3Vandp=lmA/V*. the explained d.c.-behaviour can be shown to be in good agreement with already known a.c.-MOSFET features. The last term of relation (13) equals 0.5 V,i( 1 + y) for small values of Vd with respect to Vz. This dependence of V, on Vd can be obtained also if we assume the actual oxide capacitance C,, to be equally divided into a gate-to-source and a gate-to-drain capacitance. The relation between V, and V,, that can be derived from eqn (13), however, is no longer linear, which is in agreement with the already known de- pendence of the differential gate-to-source and gate- to-drain capacitance of a conventional MOSFET on the applied voltages[6,7]. In the saturated mode the differential gate-to-drain capacitance of a conventional MOSFET becomes zero, which corresponds to the case that V, is inde- pendent of Vk 4. EXPERIMENTAL In the practical situation the first discussed case with dominating parasitic capacitances can be avoided as much as possible by optimizing the device fabrication process. The second mentioned case without effective para- sitic capacitances will never be reached because bond- ing wires and package leads easily introduce parasitic capacitances in the same order of magnitude as the total oxide capacitance C,,,. Measured IsVd charac- teristics will therefore always be a combination of the theoretical curves given in the Figs. 3 and 4. To verify the calculated results we have measured the IsVd characteristics of MOSFETs with uncon- nected gate of the type Philips-BFR 29. Results are given in Fig. 5, curve A. In the same figure the curves B, C and D are shown with V, = 0, Vg = 0.15 Vd and Vg = 0.5 Vd re- spectively, to be able to explain the floating gate characteristic. The ratios between V, and Vd are realized by 0- 0 2 4 6 8 - Vd [Volt] Fig. 5. Experimental IaVd characteristics with A: floating gate, B: V, = 0, C: V, = 0.15 Vd and D: V, = 0.5 V,. connecting different resistors between the gate-, drain- and source-terminals, simulating well defined capacitances. For small values of the drain-source voltage, curve A behaves like curve D with V, = 0.5 Vd. The floating gate characteristic differs more and more from curve D for increasing values of Vd, and for very large drain-source voltages the slopes of curve A and C with VK = 0.15 Vd are nearly the same. Curve A can thus not be described with a constant ratio between V, and Vd, and also does not fit to one of the curves given in Fig. 4. Therefore we conclude that the gate-source and gate-drain capacitance are neither very large with respect to the actual oxide capacitance, nor equal to zero. The experimental curve can not be explained by one of the two extreme cases. Although the measured curve A can be explained qualitatively, we have to combine the theories, given for the two extreme situations to describe the total curve in an exact way. This however, will result in an equation much more complicated than relation (13). Hence, it is more useful to compare the measured device characteristics with simulated results. For this purpose we have used the Spice 2 simulation pro- gram, developed at University of California, Ber- keley, U.S.A. First of all we have chosen realistic values for the channel length L, the channel width W, the oxide capacitance per unit area C,,O, and the threshold voltage V, of the Philips-BFR 29. The drift mobility of carriers in the channel p, and the substrate doping NIub are varied to obtain a simulated curve maximally fitted to the measured curve B of Fig. 5. In this way we determined: L = 10 pm, W = 5200 pm, CoXO = 1.7 t 10m4 F/m*, V, = - 3 V, p = 600 cm’/ Vs and Nsub = 1.8 IO” cm’. All other parameters used in the Spice simulation are chosen large or small, to be of negligible influence Application of a floating gate on d.c.-MISFET characteristics 315 0 2 4 6 8 [volt] Fig. 6. Simulated I,V, characteristics with A’: C,,= 1 pF and C,, = 0 pF, B’: V, = 0, C’: Vg = 0.15 V, and D’: V, = 0.5 VII. on the performance of the characteristics. The corre- sponding value of the actual oxide capacitance C,, is 8.9 pF. In our calculations the voltage VUP of the upper plate is supposed to be equal to zero. The capaci- tances C,, and C,, are thus connected in parallel and therefore can be considered as one capacitance C,, between gate and source. In the Spice simulation program leakage resistors between gate-, drain- and source-terminals must have finite values. These resistors introduce, together with the capac- itances C,,,v, C,, and C,,,, a time constant in the order of seconds. To simulate the d.c. Z,V, characteristics we therefore have used a transient analysis. Results of the simulation are shown in Fig. 6. The parasitic capacitances C,, and Cgd, as given in Fig. 2, are simulated by external capacitances, connected be- tween the drain-gate, and source-terminals. The drain-source voltage Vd is increased with 0.1 V/psec. Curve C’ is obtained with C,,= 100 pF, and C,,$ = 560 pF, and curve D’ with C,, = 100 pF and C,, = 100 pF. Curve A’ of Fig. 6 is fitted to curve A of Fig. 5 by varying the values of the capacitances C,, and C,,. The simulations are strongly influenced by the value of the gate to drain capacitance and are rather insensitive to variations of the gate to source capac- itance. Curve A’, shown in Fig. 6 is obtained with C,,, = 1 pF and C,, equal to zero. The error of the simulated results is always less than 8% with respect tot he measured results, which is sufficiently accurate for our purpose. 5. CONCLUSIONS By using first order MOSFET theory the influence of a floating gate on d.c.-MISFET characteristics can be described in an exact way for two extreme situ- ations. In the first case parasitic capacitances are dominating, in the second they are equal to zero. The description for all other cases will lead to rather complicated equations, but the characteristics can easily be calculated by the Spice 2 simulation program. Acknowledgemenrs-The authors wish to thank Professor 0. W. Memelink and Dr. H. Wallinga for their helpful discussions and stimulating suggestions. 1. 2. 3. 4. 5. 6. 7. REFERENCES D. Frohman-Bentchkowsky, Solid-St. Electron. 17, 517-529 (1974). R. G. Swartz, Ph.D. dissertation, Stanford Electron. Lab., Stanford Univ., Stanford, CA, Chap. 4, Tech. Rep. G651-1, June 1979. R. L. Smith et al., J. Electrochem. Sot. 127, 1599-1603 July (1980). J. A. van Nielen and 0. W. Memehnk, Philips Res. Repts 22, 55-71 (1967). S. M. Sze, Physics of Semiconductor Devices. Wiley, New York (1969). J. E. Meijer, RCA Rev. 32, 42-63 (1971). M. B. Das, Solid-St. Electron. 11, 305-322 (1968). SSE Vol. 27, No. 4-B 

The consequences of the application of a floating gate on d.c.-MISFET characteristics

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