Presents a Gate Array for implementing electronic circuitry to control multi-electrode arrays, which consist of 128 microelectrodes. The chip contains multiplexers, current sources and buffer amplifiers in CMOS technolog

Frieswijk, Theo A.

Kerkhoff, Hans G.

Lippe, Karel

Rutten, Wim L.C.

English

University of Twente Research Information

1995 IEEE-EMBC and CMBEC Theme 5:  Neuromuscular Systems/Biomechanics Control electronics for a neuro-eIectronic interface implemented in a Gate Array The0 A. Frieswijk, Wim L.C. Rutten, Hans G. Kerkhoff, and Karel Lippe Institute for Biomedical Technology / MESA Research Institute Faculty of Electrical Engineering, Biomedical Engineering Division / Division of IC Technology and Filectronics, University of Twente, P.O. Box 217,7500 AE Enschede, The Netherlands Abstract - We present a Gate Array for implementing electronic circuitry to control multielectrode arrays, which consist of 128 microelectrodes. The chip contains multiplexers, current sources and buffer amplifiers in CMOS technology. INTRODUCTION For selective intraneural stimulation we intend to use a three-dimensional array of 128 electrodes [lf. A major step in the development of the device is the contacting technology. Becaw the electrode contacts at the backside measwe only 55x55 pm and have a heart-to-heart spacing of 120 pm, standard technologies such as Ultrasonic Wire Bonding cannot be used. As a solution to this problem we developed a flipchip technique to connect the 3D device to a CMOS chip (described in a separate abstract). Figure 1 shows a schematic overview of the resulting structure. At the center, the chip contains a 4x32 m y  of metal pads to which the multi electrode can be connected. In this paper we present the design of a suitable CMOS chip. Because designing and realizing a N 1  custom CMOS chip is a costly and timeconsUming process, we used a gate array for implementation of the eIectronic circuitry. The gate array (GA2001) contains 1074 cells of 4 PMOS and 4 NMOS transistors each. The aluminum interconnect layer is designed specifically for the application, all other layers are already present. Designing an application chip is merely defining the necessary connections between transistors within the basic cells, and the connections between the cells. Figure 1: Schematic overview of a CMOS chip Canying a threedimensid m y  of 128 microelectrades, which can be inserted into a m 8  0-7803-2475-7197 $1 0.00 0 1 9 9 7  IEEE 1103 METHODS The CMOS chip in our application should meet the following demands: 0 provide multiplexing possibilities 0 provide current sources for stimulation with biphasic e provide buffer amplifiers for recording of neural signals 0 minimize number of leads e provide possibility of solder bumping 0 be sufficiently small for implantation 0 allow implementation in a Gate Array current pulses The Gate Array is primarily designed to contain digital electronic circuitry. The main problems in the design therefore occw in the analog parts (current soufces and amplifiers). The current sou~ces should be able to produce a biphasic current pulse, with either amplitude or duration adjustable. Pulse width modulation is easier to implement in the gate array, because (digital) switches can be used. The (constant) current amplitude should be several tens of microamperes, while the duration should range from 0 to approximately 100 ps, in steps of 1 ps. The amplifiers should primarily buffer the measured neural signals, The output impedance should be lower than 1 kn . Amplification of the signals is of lesser concern. For neural action potentials the power spectrum ranges to at most 10 kHz, which should thus be the bandwidth of the amplifiers. Taking the bandwidth too high will increase the Total Harmonic Distortion and increase the output noise level. The noise level should be less than 1 pV rms over the full bandwidth. The Gate Array measures 6x6 mm, and will need 15-20 COM~C~~OIIS to the outer world. For acute experiments this is acceptable, but for long-term implantations a smaller number of leads is desirable. Because only a limited number of transistors is available, limitations are imposed on the design. The 128 electrodes are split into 8 sections of 16 electrodes each. Every section has its own control elwonics. A layout of the design for one group is shown in figure 2. TonUdo~mmonIn F i p  2 Multiplexing electronicS, ament sources and a M a  amplifier for a group of 16 electrodes RESULTS Because the Gate Array was designed primarily for digital purposes, implementing the multiplexers and switch control registers is straightforward. NANDs and INVERTORS were used to construct a 16 to ldecoder, one for each of the 8 groups in the design. From testing, these proved to work up to clock frequencies of at least 20 MHZ, which should be sufficient for our application. A control register for the switches of the current sources also works very well. Less common is the use of analog elements in the Gate array, such as our amplXer and current source. The problems here arise not only from the arrangement in basic cells (with some transistors already connected), but also from lack of accurate model parameters for simulation of the analog circuits. Further complications arise from the limited supply voltage (0-5 V) and especially the long polysilicon connection lines that must frequently be used. Figure 3 shows the design of the current sources in CMOS technology. First note that the electrodes are always halfway between Vdd (5 V) and Ground, because otherwise no biphasic stimulation pulses would be possible. These biphasic stimulation pulses are preferable because of the lower reversible charge injection limit [3] as compared to monophasic stimulation pulses. Vdd Figure 3: C u m  soufces in CMOS technology. Nota that the electrode potential is halfivay between Vdd and Ground, in order to allow biphasic stimulation patterns IFath: cathodic c u r r ~ ,  Ian: anodic current 0 1 2 3 4 5 6  Time (ps) Figure 4 switching behavior of the current sources (simulated). See description ,textfora In figure 4, the simulated switching behavior of the current sources is shown. The voltage over a load of 50 kR was calculated as a function of time. At t"0, the 'electrode' is at 2.5 V, haIfway Vdd and Ground. From t=O.5 ps until t-3.0 ps the cathodic source is switched on, from t-3 ps until ~ 5 . 5  ps the anodic source is switched on. The nominal current values are 10.4 pA (anodic) and 11.9 pA (cathodic); source impedance was 35.7 MR and 166 Mn resp. The maximum switching delay was 0.78 ps. For a larger load (i.e. a larger electrode impedance) the switching delay becomes larger: at a load of 100 kC1, it is 2.30 ps. The combination of a Gate Array for realization of the electronics with a flip-chip technique (accompanying paper) provides a widely applicable contacting technique. We feel it might be of use in many other applications where electrode arrays must be contacted. ACKNOWLEDGMENT The authors wish to thank J.W.A. van Dorsten and T.H Humme1 for designing the Gate Array layout, and the IC Technology and Electronics group at MESA for realization of the Gate Arrays. REFERENCES [I] T A  Frieswijk and W.LC. Rutten, "Three-dimensional neuroelectronk interface for peripheral nerve stimulation and recording: realization steps and contacting technology," Proc. 16th Ann. Int. Cor$ LEEE EUBS, pp. [Z] W.LC. Rutten, T.A. Frieswijk, J.P.A. Snit, T.H. Rozijn, and J.H. Meier, "3D Neuro-electronic ioterface &Vices for neuromuscular corrtrol: Design studies and realisation steps," Biosensors andBfoeZectronics, vol. 10, pp. [3] W.P. Agnew and D.B. Mccreeiy (eds.), Neural prostheses. Fundamental 808-809,1994 141-153.1995 sfudies. Prentice Hall, New Jersey, 1990 1104 

Control electronics for a neuro-electronic interface implemented in a gate array

NARCIS 

3D Neuro-electronic ioterface &Vices for neuromuscular corrtrol: Design studies and realisation steps,&quot;

Three-dimensional neuroelectronk interface for peripheral nerve stimulation and recording: realization steps and contacting technology,&quot;

http://purl.utwente.nl/publications/17342

Control electronics for a neuro-electronic interface implemented in a gate array

Abstract

Similar works

Full text

Available Versions

University of Twente Research Information

NARCIS