This paper will describe the way a VLSI circuit project is intended to be used for training in the Postgraduate School for Computer Aided Electrical Engineering in Bucharest, Romania. The stress will be focused on the main design steps, on the use of various CADENCE EdgeTM VLSI design environment facilities, and on strong team collaboration stimulatio

Guyot, A.

Ioan, D.C.

Lazarescu, Mihai Teodor

Romanian

PORTO Publications Open Repository TOrino

Educational aspects of VLSI training at postgraduate level

This paper will describe the way a VLSI circuit project is intended to be used for training in the Postgraduate School for Computer Aided Electrical Engineering in Bucharest, Romania.  The stress will be focused on the main design steps, on the use of various CADENCE EdgeTM VLSI design environment facilities, and on strong team collaboration stimulation

Guyot A.

Ioan D. C.

LAZARESCU, MIHAI TEODOR

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

04 August 2020POLITECNICO DI TORINORepository ISTITUZIONALEEducational aspects of VLSI training at postgraduate level / Guyot A.; Lazarescu M.T.; Ioan D.C.. - ELETTRONICO. -(1993), pp. 104-109. ((Intervento presentato al convegno 4th EUROCHIP Workshop tenutosi a Toledo, Spain nelOctober 1993.OriginalEducational aspects of VLSI training at postgraduate levelPublisher:PublishedDOI:Terms of use:openAccessPublisher copyright(Article begins on next page)This article is made available under terms and conditions as specified in the  corresponding bibliographic description inthe repositoryAvailability:This version is available at: 11583/2507494 since:Eduational aspets of VLSI training atpostgraduate levelProf.dr. Alain GUYOTInstitut National Polytehnique du GrenobleMihai T. LAZARESCU\POLITEHNICA" University of BuharestConf.dr.ing. Daniel C. IOAN\POLITEHNICA" University of BuharestFaultatea de Eletrotehnia, sala EB206,Spl. Independentei 313, 77206 Buuresti,ROM^ANIAABSTRACTThis paper will desribe the way a VLSI iruit projet is intended to be used for training inthe Postgraduate Shool for Computer Aided Eletrial Engineering in Buharest, Romania.The stress will be foused on the main design steps, on the use of various CADENCE EdgeTMVLSI design environment failities, and on strong team ollaboration stimulation.I { INTRODUCTION | The Romanian PSCAEE shoolThe TEMPUS Joint European Projet JEP 2717, entiteled \Initiation of Formal Training in Com-puter Aided Eletrial Engineering in Romanian Universities" is oordinated by Polytehni University ofBuharest and has as ontrator COREP { Politenio di Torino. Among other institutions, the partnersinterested in VLSI iruit design are: INPG-CMP, Universita di Genova, National Tehnial Universityof Athens, Thames Valley University and ISEN Lille. The projet is naned mainly by CEC, having forthe three aademi years 1991-1994 a total budget of 586,000 ECU.The main goals to of this projet are: establishing a Postgraduate Training Center of CAD/CAE in Eletrial Engineering (PSCAEE) atPolytehni University of Buharest; organizing and operating a CAD/CAE laboratory and assoiated doumentation enter; urriulum development and textbooks editing; EC-RO mobility program for professors and students; organization of a workshop in CAD/CAE, with international partiipation.The postgraduate enter of CAEE ould train about 20 high level speialists annually. Two maindiretions of study are available: eletromagneti eld modelling and (miro)eletroni systems design.Boths diretions' urriulum inludes a restrited number of ompulsory ourses (assuring theoretialbakground and Unix operating system knowledges) and a large hoie of optional ourses. In addition,individual studies and omputer-laboratory works are inluded in the student's training. During the twoyears of part-time study, the students will have to ahieve both a mid-term projet and a graduationprojet working in Polytehni University Buharest or in one of the partners' university.In the frame of mobility program of TEMPUS JEP 2717, ve Romanian professors and one graduatestudent spent eah 3-6 months at INPG-CMP, Frane. Three speialists from INPG visited PolytehniUniversity of Buharest. Following this program, 14 volumes of textbooks, summing more than 3,500pages were edited and printed in 30 opies.The ontat with the JEP partner representative, Dr. Bernard Courtois from INPG-CMP oered tothis newly founded Romanian CAEE training enter from Polytehni University Buharest the oppor-tunity to apply and to be aepted as partner in the EUROCHIP sheme. The suess of this TEMPUSJEP allows to improve essentialy the VLSI systems design training at Polytehni University. Softwarepakages for VLSI systems design suh as Cadene-Edge, Hilo and HSpie were aquired by JEP 2717using the EUROCHIP oer and were instaled for PSCAEE laboratory on workstations (DECStation5000/25, SUN LX, HP-Apollo 9000/710, and 705) purased by JEP budget.The organization of the Postgraduate Training Center in CAD/CAEE is the rst attempt of this kindin Romania.As for every begin, there were many diÆulties onsisting mainly in the lak of information in Romaniaregarding: Unix-RISC workstation (software and hardware); appropriate books and periodials, andimportant delay in CAD tools delivery due to restritions imposed for advaned tehnology transfertowards Eastern European ountries.Among the suesses, one of the most important and enouraging is the fruitful ollaboration withthe JEP partners representative. The joint with EUROCHIP sheme is an exelent opportunity to beintegrated in the European eorts aimed to improve VLSI systems design training.II { The laboratory workThe students will have free aess to the whole laboratory doumentation. They will reeive thetheme, the work sheduling and will be helped with hints whenever neessary. There is no ontinouslysupervising provided for the lab. A few hours several days a week, a qualied person will be available forinquiries and help.A theme suitable for this almost self-teahing working method has to be simple enough to be easyin-deepth understood by eah student, and a splittable one in order to allow a high degree of paralleldevelopment by assigning the subparts to separate teams.Sine mathematial operators are inherently involved in data proessing irrespetive of the data type,they are to be found in almost every proessor. Moreover, the overall automaton performanes aredenitevely inuened by the quality of the used operators.Given the above onsiderations, we intend to propose as laboratory work for the VLSI division ofPSCAEE a design of a fast binary divider.The internal struture of the proposed divider an easily be splitted into several quasiindependentlaboratory works. As the nal goal is to put all the piees together into the full ustom layout of thedivider, the laboratory work implies also a permanent ollaboration among students to oordinate theirimplementations, that beames more tight as the projet is narrowing the end phase. Also, optimizationsin shematis and layout for eah part as well as for the whole design have to be realized, as the lowomputation delay and a minimum area on siliium are important riteria for the iruit's quality.III { Ciruit's strutureTwo operands are needed as divider's input: the dividend and the divisor, both written in a standardbinary notation, that is using only 0 and 1 as binary digit values. They are supposed normalized binarynumbers, aording to IEEE 754-1985 standard. Internal omputations inside the divider are done in abinary borrow-save notation, that is using  1, 0, and 1 as possibles values for eah binary digit. Thequotient is then omputed in the same redundant notation. This is why an extra blok was added toperform the quotient onversion from the redundant notation to the standard binary one, supposed tobe used in the rest of the iruitry.The divider is omposed of three parts (g. 1), eah of them playing a distint role in internal dataow: the head ell reeives as inputs the three MSB of the partial remainder, written in redundantnotation. The ell has three roles at its turn.TAIL CELLd r r- +-qq-q+ q+s+ s-TAIL CELLd r r- +-qq-q+ q+s+ s-TAIL CELLd r r- +-qq-q+ q+s+ s-TAIL CELLd r r- +-qq-q+ q+s+ s-TAIL CELLd r r- +-qq-q+ q+s+ s-TAIL CELLd r r- +-qq-q+ q+s+ s-TAIL CELLd r r- +-qq-q+ q+s+ s-TAIL CELLd r r- +-qq-q+ q+s+ s-TAIL CELLd r r- +-qq-q+ q+s+ s-TAIL CELLd r r- +-qq-q+ q+s+ s-TAIL CELLd r r- +-qq-q+ q+s+ s-TAIL CELLd r r- +-qq-q+ q+s+ s--+ +-rHEAD CELLr-2- r-2+ r-1 -1+- r0- r0+qqqqs--1 s-1 s0-+-+ +-rHEAD CELLr-2- r-2+ r-1 -1+- r0- r0+qqqqs--1 s-1 s0-+-+ +-rHEAD CELLr-2- r-2+ r-1 -1+- r0- r0+qqqqs--1 s-1 s0-+-+ +-rHEAD CELLr-2- r-2+ r-1 -1+- r0- r0+qqqqs--1 s-1 s0-+a a ad1 1 d2 2 d3 3FINAL REMAINDERQUOTIENT CONVERSION0MSB LSBaQUOTIENT IN STANDARD BINARY NOTATIONCritical pathQ =R0= AADFigure 1: the blok shemati of a 4 bit dividerFirst it omputes a quotient digit. This quotient digit is used then by the subsequent tail ells inthe same row to hoose the operation to exeute on the rest of the partial remainder digits | anaddition, a subtration, or nothing.The seond role of the head ell is to do that omputation on the MSBs of partial remainder as thetail ells do with the rest of the remainder's bits. The MSB of the normalized divisor D is always1, so it is onsidered as an impliit onstant signal in the head ell during omputations.Finally, the head ell take advantage of the redundant notation of the partial remainder and rewriteits MSB in an equivalent form, so that the next remainder has one most signiant digit less. Thisis to avoid trunation errors when shifted one bit to the left for the next stage.The ve signals generated by the head ell (g. 1) have the following boolean expressions:q+j= r+ 2+ r  2(r+ 1r  1+ r  1r+0r 0+ r+ 1r+0r 0) ;q j= r  2+ r+ 2(r+ 1r  1+ r+ 1r+0r 0+ r  1r+0r 0) ;s+ 1= r+ 2(r+ 1+ r  1+ r+0r 0) + r  2r+ 1r  1r+0r 0;s  1= r  2(r  1+ r+ 1+ r 0r+0) + r+ 2r  1r+ 1r 0r+0;s 0= q j r+0 r 0: the tail ell reeives as inputs a digit of the divisor (in binary standard notation), a digit of thepartial remainder (in binary redundant notation), and the quotient digit omputed by the headell of its row. The tail ell's role is to perform an addition, a subtration or no-operation on itstwo input digits (one of the divisor and one of the partial remainder), aording to the value of thereeived quotient digit.The two signals generated by the tail ell, s+i 1and s isatisfy the equality:2  s+i 1  s i= r+i  r i+ (q+jdi+ q jdi) the quotient onversion blok , as the name shows diretely, has to onvert the omputed quotient inredundant notation to binary standard notation, the last notation beeing supposed to be used bythe rest of the iruit that the divider is part of. This blok is omposed from small ells disposedin a regular struture.IV { One possible laboratory work. Complexity evaluationThe students an be organized in three teams, eah team having to design one of the divider's parts:the head ell, the tail ell, and the quotient onversion blok.Clearly it seems that the head ell is the most ompliated ell with respet to the others, sine ithas to generate 5 signals, all of them using all the 6 input signals. Anyway, due to the perfet symmetryof the borrow-save notation, the q+jand q jsignals have the same struture for their expression, onlythe input signals are dierent. The same stands for s+ 1and s  1too. This means that this two pairs ofsignals will have the same shemati at transistor level, but the transistors themselves will be driven bydierent input signals. The fth head signal, s 0is generated by a very simple gate anyway.So, besides the simpler gate for the s 0signal, there are to be designed only two struturaly dierentomplex gates: one for the q+jand q jsignals, and the other for s+ 1and s  1. On the other hand, thesurfae of the head ell layout isn't a very important onstraint to be observed, beause for a n-bit dividerthere are just n head ells in the layout.In gure 1 we an see that the ritial path of the divider is passing through the head ell. Morepreisely, the omputation time of the q jand q+jsignals is very important. This is why the omplexgates whih generate this two signals have to be arefully optimized in terms of speed.The tail ell is muh smaller than the head ell. Depending on the implementation, the transistorount is two to four times smaller than in the head ell. The input signals are 5 for eah tail ell and thegenerated ones are just two. This means that the omplexity of the gates inside a tail ell is lower thanthose in the head ell. Instead, the main issue with the tail ell is the layout area, beause for a n-bitdivider the number of its tail ells is n (n   1). This makes the total area of the tail ells to representalmost all the divider's area, espeially for a large number of bits (n).The divider's ritial path runs through the tail ells too (g. 1), so that its omputation time isaeting the overall omputation speed of the whole divider. Shematis optimization for area and speedare thus mandatory for this ell.Finally, the quotient onversion blok is a rather sholasti one. It onsists of several identi ellsdisposed in a regular struture. If applied, area optimization riteria will impose however the use oftwo dierent types of ells in order to take advantage of the higher omputation speed of the quotientonversion versus quotient digits output rate. This may ompliate a whit the quotient onversion bloklayout design. Quotient onversion is done \on the y", so the main optimization for this ell is to hoosethe minimum number of rows in the quotient onversion ell based on the ratio between the omputationtime of qjsignals and the traversal time of a row of ells in the quotient onversion ell.Given the onsiderations above it shows up that the three parts of the divider's struture ould on-stitute well balaned design projets for laboratory work. The teams in harge to design the divider'sparts are stimulated to ooperate to deal eÆiently with issues like minimizing the divider's area, opti-mizing the ritial path, hoosing the rows number in the quotient onversion ell based on delays, powerdistribution, ommon ell pith, ommuniation pins position for assembling by abbutment, et.In the same time, eah of the divider's parts has its own spei hot-point. The designers of the headell will have to deal with omplex gates and the omputation time minimization for q jand q+jsignals.The tail ell layout has to be as small as possible and the omputation time for its signals minimized too.The more novies ould be grouped in the team harged to design the quotient onversion ell, whih islikely to be a good starting projet for them.For an arithmeti operator, the worst ase omputation time is the only one onsidered at performanesevaluation. The students will have to pay attention to the evaluation and minimization of the worstase delay for the ritial path signals of their ells. This implies worst ase input vetors sequenedetermination, and several shemati struture simulation.V { Some variantsThere are several implementations for the divider's ells that an be hoosed from. There are also foreah ell's shemati several hoies. Let's skim some of them.Fairly the most omplex one, the head ell an be implemented using either stati or dynami CMOSlogi. Of ourse, to eÆiently use the dynami logi major hanges in the whole divider's struture areneeded, but for an eduational purpose projet it's use may be restrited just for the head ell.The tail ell is struturally a Full Adder ompleted with a multiplexer for one of the input signals.The ell an be implemented in this blok struture fully with CMOS gates or with transmission gates.Another hoie may be to draw out the ell's shemati from the signals' truth tables, whih ase one ofthe most advantageous hoie is that using just transmission gate based multiplexers, and inverters.For the quotient onversion ell it is possible also to use a ombination of pass transistors and CMOSgates in order to minimize the transistor number.So far we disussed only about the full ustom (i.e. at transistor level) implementation of the ells.This is the most performant one, but for CAD tools teahing purposes one might onsider a standardell based design too. In this latter ase, the freedom of hoie in shemati oneption is somehowrestrited with respet to the full ustom design, and there are less optimizations to be searhed. But thestandard ell approah ombined with the Automati Plae and Route faility of CADENCE EdgeTMdesign environment is by far the fastest way to get the layout of a iruit using this CAD tool.The most time onsuming and tedious stage of the projet is ertainly the layout design if is doneby hand. This an be rended onsiderably shorter and a lot more pleasent making use of \The LayoutSynthesizer" tool (LAS), ombined with Symboli Layout Editor and Compator. This tools are bothprovided in the CADENCE EdgeTMenvironment. The LAS is able to automatially generate a symbolilayout of a ell using the transistor level shemati as its input. The generated symboli layout may befurther optimized using the Symboli Layout Editor and Compator. Of ourse, to have a more ompleteontrol over the ell's layout, one may use from start only the symboli Layout Editor and Compator,designing the symboli layout itself.VI { ShedulingDepending on the number of laboratory hours alloated for the projet and the student's knowledgelevel in miroeletronis, the theme denition an be biased either to a more automati or a more manualapproah.In any ase, the theme should ompel the hardworking student to go through and master all thefailities oered by the design environment for the given approah. Logi simulation to hek shemativalidity, eletri simulation for timing optimization, and post-layout simulations on extrated shematiswith parasitis are a must. This should be joined by the use of the various features of the Automati Plaeand Route tool or, for the other extreme, those of the LAS and Symboli Layout Editor and Compatortool.Viewing the theme's omplexity, it would be a good idea to extend the alloated laboratory hourson two semesters. The most part of the time shall be devoted by the students to iruit and layoutoneption as well as studying various optimization alternatives. This way, the omputer working timewill be eÆiently used to implement the best hoies and to learn the design environment. This meansthat there is no need to use important omputing resoures for this projet, whih is an important issuefor a poor hardware dotation lab.VII { Expeted results and ommentsThe proposed work is rather large and omplex. It should nally learly distinguish the hardworkingstudents from the others.The advantages of suh a work are important and multiples: oers the feeling of a real projet (although a small one) and ould onstitute a valuable startingexperiene for a further work in VLSI ASIC design. develop team ollaboration relationship and inter-team ooperation on various stages of the design,mainly in the oor planning phase (layout design). as a high performane iruit, this should stimulate the student's ommitment in searhing optimi-sations making use reatively of their eletronis knowledges as well as learning new ones. there is already available a CMOS stati logi implementation of the divider, whose performanesould be taken as referene by the students in order to self-evaluate their own work. This shouldmake them willing to ahieve better results, stimulating their inventivity. the division is a very well known operation, that does not need intriate speiations.Skills in using the design environment should be appreiated in the nal notation.Referenes[1℄ ANSI/IEEE, IEEE Standard for Binary Floating-Point Arithmeti, ANSI/IEEE Standard 754-1985,1985[2℄ A. Avizienis, \Signed-digit number representation for fast parallel arithmeti", IRE Transations oneletroni omputers, 10, 1961, pp. 389-400[3℄ C. Y. Chow and J. E. Robertson, \Logial design of a redundant binary adder", in Pro. 4thsym-posium on omputer arithmeti, 1978, pp. 109-115[4℄ L. Montalvo and A. Guyot, A hybrid radix-4 divider with operand saling. Unpublished internalpaper, TIMA Grenoble, 1993[5℄ I. Moussa, A. Skaf and A. Guyot, Design of a GaAs redundant divider, VLSI'93 Grenoble, 1993[6℄ I. Moussa, A. Guyot and P. Rost, Design and omparison of GaAs and CMOS dividers, ESSIRC'93,Sevilla, 1993[7℄ J. M. Muller, Arithmetique des ordinateurs, Paris: Masson 1989[8℄ J. E. Robertson, \The orrespondene between methods of digital division and multiplier reodingproedures", IEEE Transations on omputers, C-19 No8, 1970[9℄ N. Weste & K. Eshraghian, Priniples of CMOS VLSI Design, Reading Massahusetts: Addison-Wesley Publishing Company, 1985[10℄ J. William & V. C. Hamaher, \A linear-time divider array", Canadian Eletrial Engineering Jour-nal, Vol. 6 no4, 1981[11℄ Mead & Conway, Introdution to VLSI systems, Addison-Wesley Publishing Company, 1980

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Educational aspects of VLSI training at postgraduate level

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