This paper provides a methodology that leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software syste

Baranowski, R.

Di Carlo, Stefano

Hatami, N.

Imhof, M.E.

Kochte, M.A.

Prinetto, Paolo Ernesto

Wunderlich, H.J.

Zoellin, C.G.

English

PORTO Publications Open Repository TOrino

System Reliabil ity Evaluation Us-
ing Concurrent Multi-Level Simu-
lation of Structural Faults
Authors: Kochte M. A., Zoellin C. G., Baranowski R., Imhof M. E., Wunderlich H. J., Hatami N., Di 
Carlo S., Prinetto P.,
Published in the Proceedings of the IEEE International Test Conference (ITC), 31 Oct. - 5 Nov. 
2010, Austin (TX), USA.
N.B. This is a copy of the ACCEPTED version of the manuscript. The final 
PUBLISHED manuscript is available on IEEE Xplore®:
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5699309
DOI: 10.1109/TEST.2010.5699309
© 2000 IEEE. Personal use of this material is permitted. Permission from IEEE must be 
obtained for all other uses, in any current or future media, including reprinting/republishing 
this material for advertising or promotional purposes, creating new collective works, for resale 
or redistribution to servers or lists, or reuse of any copyrighted component of this work in 
other works.
!Politecnico di Torino
System Reliability Evaluation Using Concurrent
Multi-Level Simulation of Structural Faults
Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski,
Michael E. Imhof, Hans-Joachim Wunderlich
University of Stuttgart
Institute of Computer Architecture and Computer Engineering
Pfaffenwaldring 47
D-70569 Stuttgart, Germany
Nadereh Hatami, Stefano Di Carlo,
Paolo Prinetto
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
I-10129 Torino TO, Italy
Abstract—This paper provides a methodology that leverages
state-of-the-art techniques for efficient fault simulation of struc-
tural faults together with transaction level modeling. This way it
is possible to accurately evaluate the impact of the faults on the
entire hardware/software system.
I. INTRODUCTION
Structural faults model the consequences of physical defects
at the gate and logic level. To validate the reliability of a
system, fault injection is often adopted. For structural faults,
fault injection must be done on a gate-level model at which
simulation is usually not feasible due to its size and availabil-
ity. Instead, multilevel simulation techniques are used. These
techniques use a model at low abstraction level such as gate
level for the fault injection and a model at higher abstraction
level for the evaluation of the consequences [1].
This paper presents an integrated fault simulation environ-
ment for structural faults injection into a multi-level simulation
at gate- and transaction level. It is based on a structural fault
model with an efficient concurrent fault simulator at gate level.
Error propagation is done at transaction level with a rollback
mechanism that is simple to use with existing transaction level
simulator kernels, yet allowing concurrent error propagation.
The approach is adaptive and selects the gate-level model just
if a component is subject to fault injection. It also combines
the precision of gate-level simulation with the high simulation
speed of transaction level.
II. MULTI-LEVEL SYSTEM MODEL
A TLM of the system is augmented by precise gate-level
models of components which are subject to fault simulation
and analysis. Fault simulation of a gate-level model determines
which faults cause errors at the outputs. For this subset of
visible faults, functional error propagation is performed at
transaction level. The propagated error is then evaluated at
system level to check whether the fault eventually results in a
system failure, i.e., an error observable in the application.
The system and target application are modeled at transaction
level. To investigate hardware blocks and cores, gate-level
fault simulator instances are created using gate-level models.
Transactions directed to these cores are handled by gate-level
wrappers which translate transactions into the appropriate pin-
and cycle-accurate communication protocol of the core and
vice versa. The data is then handed to the fault simulator.
The wrapper provides the environment and infrastructure to
the gate-level component and processes the fault detection
information and fault propagation requests of the sequential
fault simulator.
To achieve high accuracy, the wrapper properly manages
unknown and conflicting values. That cannot easily be rep-
resented in a regular TLM flow. Several alternatives are
available depending on either pessimistic or optimistic bound
on targeted system reliability.
III. IMPLEMENTATION AND EVALUATION
The system has been implemented based on the sequential
gate level fault simulator Hope [2], OSCI SystemC 2.2 and
TLM-2.0 libraries. The evaluation concentrates on the fault
classification accuracy as well as the run-time for two different
applications executed on an AMBA based SoC with a LEON3
processor, hardware accelerator cores for Triple-DES (Data
Encryption Standard) encryption and a two-dimensional dis-
crete cosine transformation core. As target hardware/software
applications, the Tripe-DES encryption of data blocks, and
the JPEG encoding of images, are considered. To benefit from
the parallel execution of simulator instances, the experiments
were run on a multiprocessor system with 8 Intel Xeon CPUs
running at 2.67 GHz and with 48 GB of RAM.
To integrate the Hope fault simulator into the SystemC sim-
ulation environment, C++ wrappers have been implemented
for the cores. Separate instances of the Hope fault simulator
are dynamically created for the considered gate level models.
Experimental results gathered on several case studies showed
a match of 99.8
ACKNOWLEDGMENT
This work has been supported by a Vigoni grant of the
German Academic Exchange Service (DAAD).
REFERENCES
[1] R. Leveugle, D. Cimonnet, and A. Ammari, “System-level dependability
analysis with RT-level fault injection accuracy,” in 19th IEEE Interna-
tional Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT),
2004, pp. 451–458.
[2] H. K. Lee and D. S. Ha, “Hope: An efficient parallel fault simulator for
synchronous sequential circuits,” in Proc. ACM/IEEE Design Automation
Conference (DAC), 1992, pp. 336–340.


Hope: An efﬁcient parallel fault simulator for synchronous sequential circuits,” in

System-level dependability analysis with RT-level fault injection accuracy,”

System Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults

Michael A. Kochte

Christian G. Zoellin

Rafal Baranowski

Michael E. Imhof

Hans-Joachim Wunderlich

Nadereh Hatami

Stefano Di Carlo

Paolo Prinetto

Crossref

System reliability evaluation using concurrent multi-level simulation of structural faults

This paper provides a methodology that leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software system

Kochte, M. A.

Zoellin, C. G.

Imhof, M. E.

Wunderlich, H. J.

DI CARLO, STEFANO

PRINETTO, Paolo Ernesto

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

29 November 2022POLITECNICO DI TORINORepository ISTITUZIONALESystem Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults / Kochte, M. A.; Zoellin, C. G.;Baranowski, R.; Imhof, M. E.; Wunderlich, H. J.; Hatami, N.; DI CARLO, Stefano; Prinetto, Paolo Ernesto. -ELETTRONICO. - (2010). ((Intervento presentato al convegno IEEE International Test Conference (ITC) tenutosi aAustin (TX), USA nel 31 Oct.- 5 Nov. 2010 [10.1109/TEST.2010.5699309].OriginalSystem Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural FaultsPublisher:PublishedDOI:10.1109/TEST.2010.5699309Terms of use:openAccessPublisher copyright(Article begins on next page)This article is made available under terms and conditions as specified in the  corresponding bibliographic description inthe repositoryAvailability:This version is available at: 11583/2380374 since: 2016-09-16T17:40:43ZIEEESystem Reliabil ity Evaluation Us-ing Concurrent Multi-Level Simu-lation of Structural FaultsAuthors: Kochte M. A., Zoellin C. G., Baranowski R., Imhof M. E., Wunderlich H. J., Hatami N., Di Carlo S., Prinetto P.,Published in the Proceedings of the IEEE International Test Conference (ITC), 31 Oct. - 5 Nov. 2010, Austin (TX), USA.N.B. This is a copy of the ACCEPTED version of the manuscript. The final PUBLISHED manuscript is available on IEEE Xplore®:URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5699309DOI: 10.1109/TEST.2010.5699309© 2000 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.!Politecnico di TorinoSystem Reliability Evaluation Using ConcurrentMulti-Level Simulation of Structural FaultsMichael A. Kochte, Christian G. Zoellin, Rafal Baranowski,Michael E. Imhof, Hans-Joachim WunderlichUniversity of StuttgartInstitute of Computer Architecture and Computer EngineeringPfaffenwaldring 47D-70569 Stuttgart, GermanyNadereh Hatami, Stefano Di Carlo,Paolo PrinettoPolitecnico di TorinoDipartimento di Automatica e InformaticaCorso Duca degli Abruzzi 24I-10129 Torino TO, ItalyAbstract—This paper provides a methodology that leveragesstate-of-the-art techniques for efficient fault simulation of struc-tural faults together with transaction level modeling. This way itis possible to accurately evaluate the impact of the faults on theentire hardware/software system.I. INTRODUCTIONStructural faults model the consequences of physical defectsat the gate and logic level. To validate the reliability of asystem, fault injection is often adopted. For structural faults,fault injection must be done on a gate-level model at whichsimulation is usually not feasible due to its size and availabil-ity. Instead, multilevel simulation techniques are used. Thesetechniques use a model at low abstraction level such as gatelevel for the fault injection and a model at higher abstractionlevel for the evaluation of the consequences [1].This paper presents an integrated fault simulation environ-ment for structural faults injection into a multi-level simulationat gate- and transaction level. It is based on a structural faultmodel with an efficient concurrent fault simulator at gate level.Error propagation is done at transaction level with a rollbackmechanism that is simple to use with existing transaction levelsimulator kernels, yet allowing concurrent error propagation.The approach is adaptive and selects the gate-level model justif a component is subject to fault injection. It also combinesthe precision of gate-level simulation with the high simulationspeed of transaction level.II. MULTI-LEVEL SYSTEM MODELA TLM of the system is augmented by precise gate-levelmodels of components which are subject to fault simulationand analysis. Fault simulation of a gate-level model determineswhich faults cause errors at the outputs. For this subset ofvisible faults, functional error propagation is performed attransaction level. The propagated error is then evaluated atsystem level to check whether the fault eventually results in asystem failure, i.e., an error observable in the application.The system and target application are modeled at transactionlevel. To investigate hardware blocks and cores, gate-levelfault simulator instances are created using gate-level models.Transactions directed to these cores are handled by gate-levelwrappers which translate transactions into the appropriate pin-and cycle-accurate communication protocol of the core andvice versa. The data is then handed to the fault simulator.The wrapper provides the environment and infrastructure tothe gate-level component and processes the fault detectioninformation and fault propagation requests of the sequentialfault simulator.To achieve high accuracy, the wrapper properly managesunknown and conflicting values. That cannot easily be rep-resented in a regular TLM flow. Several alternatives areavailable depending on either pessimistic or optimistic boundon targeted system reliability.III. IMPLEMENTATION AND EVALUATIONThe system has been implemented based on the sequentialgate level fault simulator Hope [2], OSCI SystemC 2.2 andTLM-2.0 libraries. The evaluation concentrates on the faultclassification accuracy as well as the run-time for two differentapplications executed on an AMBA based SoC with a LEON3processor, hardware accelerator cores for Triple-DES (DataEncryption Standard) encryption and a two-dimensional dis-crete cosine transformation core. As target hardware/softwareapplications, the Tripe-DES encryption of data blocks, andthe JPEG encoding of images, are considered. To benefit fromthe parallel execution of simulator instances, the experimentswere run on a multiprocessor system with 8 Intel Xeon CPUsrunning at 2.67 GHz and with 48 GB of RAM.To integrate the Hope fault simulator into the SystemC sim-ulation environment, C++ wrappers have been implementedfor the cores. Separate instances of the Hope fault simulatorare dynamically created for the considered gate level models.Experimental results gathered on several case studies showeda match of 99.8ACKNOWLEDGMENTThis work has been supported by a Vigoni grant of theGerman Academic Exchange Service (DAAD).REFERENCES[1] R. Leveugle, D. Cimonnet, and A. Ammari, “System-level dependabilityanalysis with RT-level fault injection accuracy,” in 19th IEEE Interna-tional Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT),2004, pp. 451–458.[2] H. K. Lee and D. S. Ha, “Hope: An efficient parallel fault simulator forsynchronous sequential circuits,” in Proc. ACM/IEEE Design AutomationConference (DAC), 1992, pp. 336–340.

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System Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults

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