Aiello, Orazio

Fiori, Franco

English

AIELLO, ORAZIO

FIORI, Franco

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

05 August 2020POLITECNICO DI TORINORepository ISTITUZIONALEInvestigation on the Susceptibility of Integrated Current Sensors to EMI / AIELLO O.; FIORI F.. - STAMPA. - (2009), pp.33-37. ((Intervento presentato al convegno EMC Compo 09 tenutosi a Toulouse nel nov. 2009.OriginalInvestigation on the Susceptibility of Integrated Current Sensors to EMIPublisher:PublishedDOI:Terms of use:openAccessPublisher copyright(Article begins on next page)This article is made available under terms and conditions as specified in the  corresponding bibliographic description inthe repositoryAvailability:This version is available at: 11583/2291474 since:university of toulouseDesign of a new MagFET-based Integrated Current Sensor Robust to EMI  Orazio Aiello Franco Fiori EMC Competence Center Microelectronics EMC Group, Istituto Superiore M. Boella (ISMB) Eln. Dpt., Politecnico di Torino, Via P. C. Boggio 61, Turin, Italy C.so Duca degli Abruzzi 24, Turin, Italy aiello@ismb.it franco.fiori@polito.it   Abstract − This paper deals with the susceptibility to electromagnetic interference of CMOS integrated current sensors for power transistor current monitoring. Conventional integrated solution are first considered, hence a new integrated current sensor based on the Hall effect in a split-drain MOS transistors (MagFET) is proposed.  The susceptibility to radio frequency interference of a conventional (wired) current sensor and that of the MagFET-based solution is discussed. 1 INTRODUCTION Common electronic systems are usually made of several  modules that include printed circuit boards (PCBs), discrete components and integrated circuits (ICs). Power and data interconnects in such systems are usually routed through cables, which in turn behave like unintentional antennas collecting electromagnetic interference (EMI) from the surrounding environment. Although several studies have dealt with the  susceptibility of integrated circuits to EMI [1-2], such a topic is far from being completely addressed and deserves further insights. To this purpose, the paper introduces the susceptibility to radio frequency interference (RFI) of common analog, digital and power front-end circuits like those used in Application-Specific-Integrated-Circuits (ASICs), then it focuses on Smart-Power System-on-Chip [3] and in particular on the susceptibility to RFI of conventional integrated current sensors needed for power transistor current monitoring. Common circuits for current sensing use a small resistor in series with the power transistor that translates the transistor current in a voltage to be further amplified and processed. Other current sensing circuits base their operation on the current mirroring principle: a small transistor (the SenseFET [4-5]) is driven by the same gate-source voltage of the power transistor so that its drain current is proportional to the power transistor current. Such integrated current sensors show low-power dissipation, need reduced silicon area and provide reasonable accuracy. However, any current sensor electrically connected to power transistor terminals like those mentioned above, is  exposed  to  interference collected by cables. For this reason additional passive filters at printed circuit board (PCB) or at IC level are usually needed. Based on that and aiming at the design of integrated current sensors intrinsically immune to EMI, this paper describes a new current sensor based on the Hall effect, which takes place in a split-drain nMOS transistor (the MagFET) whenever it is surrounded by the magnetic field of the current to be monitored [6]. The paper is organized as follows: Section 2 describes a circuit that implements the current mirroring principle (the SenseFET circuit). Section 3 recalls how magnetic field unbalances the drain current of a splitted drain MOS transistor (MagFET) and shows the operation of the new current sensor developed in this work. Then, Section 4 shows the results of computer simulations carried out to evaluate the susceptibility of the MagFET-based current sensor. These results are compared with those of the SenseFET that operates in the same condition. Finally, in Section 5 some concluding remarks are drawn.   MOSDRIVEROV_PROT+-POWER MOSSENSEFETISENSE IXVDDVSS Fig. 1: Current sensor based on the mirroring principle. MAGFETPADPowerMosD1D2LWLID2 ID1MAGFET  Fig. 2: MagFET symbol and layout view.  0 20 40 60 80 100 12080010001200140016001800200022002400Distance [μm]B [μT] Fig. 3: Vertical Magnetic Field strength vs distance impinging the MagFET. Power transistor current Ix=1A.  2 A CONVENTIONAL CURRENT SENSOR: THE SENSEFET CIRCUIT A common way of sensing the current that flows through a power transistor consists in mirroring it by means of a circuit  like  that shown in Fig. 1, where an elementary  transistor (the SenseFET) of the same type  of those used in the power transistor is driven by the same gate-source voltage of the power transistor itself. The SenseFET drain-source voltage is kept equal  to that of the switched-on power transistor by means of a voltage follower. Such a bias circuit makes the SenseFET drain current (Isense) proportional to that of the power transistor (Ix) through a constant mirroring factor, which is given by the ratio of the two transistors areas (transistors with the same channel length are considered). To this purpose, it is worth mentioning that the accuracy of such a circuit is surely limited by the transistor mismatches, which always occurs for high mirroring factor. However, the accuracy of such a current sensor can be significantly reduced by disturbances affecting the power transistor nominal signals and, for this reason, the possibility of building up a current sensor with no electrical connection with the power transistor terminals and limited bandwidth has been investigated. To this purpose, the idea of monitoring the power transistor current by sensing the magnitude of the related magnetic field has been considered. 3 A NEW CURRENT SENSOR BASED ON THE MAGFET TRANSISTOR An alternative way of monitoring the power transistor current is that of sensing the magnetic field, which is related to such a current, through the Hall effect that takes place in the channel of a MOS transistor surrounded by the magnetic field. To this purpose, let’s consider a splitted-drain MOS transistor (MagFET) placed very close to a metal strip which carries  the current to be monitored, and let’s further  assume such a sensing transistor biased in saturation. In this condition, the power transistor current gives rise to the magnetic field that induces a Lorentz force on the electrons that flow from the source to the drain in MagFET channel: in fact, the split-drain currents are imbalanced by the Hall effect. To this purpose, previous works [7-8] have   shown   that   the    current  unbalance  (ΔI) can  be expressed as                      xcBIBI IFISBISI ==Δ ⊥                  (1)  where IB is the split-drain MOS bias current (ID2+ID1); Fc is a conversion factor defined as the ratio of the magnetic flux lines density over  the split-drain transistor to the current (Ix) flowing through the metal strip current. Furthermore, SI is the MagFET sensitivity that depends on the geometry of the device (length L and width W), and that can be written as   HHchI GWLS μ21= .  (2)   In this expression, GH is a geometrical correction factor (GH=0.676 for square transistor that maximizes the sensor sensitivity) and µHch is the Hall carrier mobility given by the product of the effective carrier mobility µn (process-based) and the Hall factor rH. This last factor is almost independent on temperature (rH = 1.05 for current sensor operating temperature dropping in the range 20°C < T < 120°C  [9]), hence current sensing circuits based on MagFET are suitable to be embedded in power transistors and smart-power system-on-chips that usually experience large temperature variations.  In this work, the conversion factor Fc that relates the normal magnetic field strength with the current Ix has been evaluated performing electromagnetic simulations for a  metal strip of thickness t=4µm and width w=10µm [7]. Computer simulations have been repeated for several metal-strip-to-MagFET distances in the range 0 - 130µm and the results are shown in Fig. 3.  On   the  basis   of   these   considerations   and VBIAS3S SVOUT2M5SSVDDVOUT1M8M7M6M4M2M1M3M10M9VBIAS2MAGFETVBIAS1VBIAS3VBIAS4VBIAS4VBIAS2IBID1VBIAS-MAGICTRL2 ICTRL1ID2 Fig. 4: Trans-resistance amplifier of the MagFET output currents.  referring to a square MagFET (W=L=10µm) and metal strip to MagFET distance Δ = 10µm, the conversion factor is equal to Fc=1.845mT/A and the overall conversion factor is about  ΔI/Ix = 2.5.10-9. On the basis of the above mentioned parameters and assuming the current to be monitored ranging from 0A to 10A, the dynamic range of the MagFET differential output current takes values in the range 0-50nA. Being this current unbalance so small a trans-resistance high-gain amplifier  (folded cascade topology) like that shown  in  Fig. 4  has  been  designed  referring  to  an   auxiliary circuit for offset cancellation like 0.35µm CMOS technology process.  This gain stage shows a trans-resistance greater than 100dBΩ and it that sketched in Fig. 5. Offset compensation is performed whenever the power transistor is switched-off and no current flows through the power transistor. In this condition, the feedback loop, which is made of a voltage comparator, a 10-bit up/down counter, a DAC converter and a fully differential trans-conductance amplifier (OTA in Fig. 5), forces the sensor differential output voltage (VOUT=VOUT2-VOUT1) to zero. In particular, with the err_signal set high, the comparator output voltage VO_comp  could be high or low depending on the offset sign. In the first case (i.e. VO_comp  high) the binary counter is enabled to count up and the compensation process start taking place, while in the second case  (i.e. VO_comp  low) the logic control signal (err_signal) is set to zero and the comparator input voltage is inverted. Also in this last case the binary counter is made counting up. The code generated by the binary counter is provided to a C-2C DAC that translated it to a voltage hence to the current imbalance ICTRL1-ICTRL2. This upset in the gain stage bias current compensates the trans-resistance output offset voltage. This compensation proceeds step-by-step as long as the comparator output voltage (VO_comp) switches from high to low,  then the binary count starts proceeding backward. Once the comparator output voltage toggles stably to the clock frequency, the compensation process is stopped and the resulting binary code, which is proportional to the amplifier input offset current, is then  stored in a binary register.  This code is constantly used during the current sensing for offset compensation purposes. Fig. 5: Block diagram of the auxiliary circuit for compensating the trans-resistance amplifier output offset voltage.  10-bitCounterup/downC-2CDACOTAB0B1B2B3B4B5B6B7B8B9err_signerr_signerr_signerr_signerr_signerr_signerr_signerr_signI-VgainComparatorckup/downVOUT2 VOUT1ICTRL2ICTRL1VO_compVBIAS-MAGMAGFETCbpCcoresubstratemodelpackagemodelCURRENTSENSORVDDVSSbias T+-50VPSVRFASICpower MOS   Fig. 6: Schematic view of the circuit including the current sensor, which has been considered for computer simulations. RFI is superimposed to the drain voltage using the DPI method.  0 5 10 15 20−80−60−40−20020406080Disturbance amplitude [V]Current sensed error (%)  max MagFETmin MagFETavg MagFETmax SenseFETmin SenseFETavg SenseFET Fig. 7: Maximum, minimum and average value of the current-sensed error by MagFET and SenseFET versus RFI amplitude. CW interference at 20MHz. 4 SUSCEPTIBILITY TO RFI OF INTEGRATED CURRENT SENSORS In this section the susceptibility to RFI of the above described current sensors added to the nominal signals of a power transistor is investigated. In particular, the case of a power transistor integrated in the same silicon die with a bunch of analog and digital blocks including a current sensor is considered, and it is assumed that all signal circuits share the same power supply rails. Analyses have been carried out referring to the schematic view of Fig. 6 that includes a 2 mm2 power transistor, the substrate parasitic model, the package parasitic model and the schematic view of the current sensor under analysis. Furthermore, all circuits of the SoC except the power transistor and the current 0 1 2 3 4 5 6−100−80−60−40−2002040Disturbance amplitude [V]Current sensed error (%)  max MagFETmin MagFETavg MagFETmax SenseFETmin SenseFETavg SenseFET Fig. 8: Maximum, minimum and average value of the current-sensed error by MagFET and SenseFET versus RFI amplitude. CW interference at 100MHz.  0 2 4 6 8 10 12−250−200−150−100−50050100Disturbance amplitude [V]Current sensed error (%)  max MagFETmin MagFETavg MagFETmax SenseFETmin SenseFETavg SenseFET Fig. 9: Maximum, minimum and average value of the current-sensed error by MagFET and SenseFET versus RFI amplitude. CW interference at 200MHz.  sensor have been roughly modeled by an on-chip capacitance connected to the power supply and ground rails. Simulations have been carried out with the power transistor switched-on and the RFI added to the drain terminal using the direct power injection method [12]. In this framework, time domain simulations were performed using ELDO (a SPICE-like simulator) and the RFI-induced upset of the current sensor output signal (Isense in the SenseFET circuit and the output voltage VOUT of the MagFET trans-resistance amplifier) has been recorded. These simulation results are shown in Figs. 7, 8, 9 where the minimum, maximum and average value of the output signal RFI-induced upset versus RFI amplitude is reported. In particular, Figs. 7, 8, 9 have been obtained considering CW interference at 20MHz, 100MHz, 200MHz respectively. With reference to these results it can be concluded that the  immunity  of   the    MagFET-based current sensor (wireless sensor)  is  significantly 106 107 108 109−140−120−100−80−60−40−200[dB V]Frequency [Hz]  VDDDrain  Fig. 10: AC analysis: RFI magnitude resulting at the switched-on power MOS drain terminal and at the current sensor power supply (VDD) referred to VSS.  greater than that of the SenseFET (wired sensor). However, it should be also noticed that both current sensors are more susceptibility to RFI in the frequency range around 100MHz. To this purpose, further analyses based on small-signal computer simulations have shown that RFI added to the power transistor drives the parallel resonance of the power supply package parasitic inductances (VDD-VSS) and the on-chip parasitic capacitance CCORE (see Fig. 6). Around this resonance (about 100MHz in the circuit under analysis) the amplitude of RFI that results added to the current sensor power-supply voltage takes magnitude comparable with that at the power transistor drain terminal, as it is highlighted by the plots in Fig. 10.   5 CONCLUSION In this work, the susceptibility to RFI of integrated sensors for power transistor current monitoring has been discussed. To this purpose, a conventional current sensor, which is electrically connected by metal strips to the power transistor terminals, has been considered. Furthermore, a new wireless current sensor, which is based on the Hall effect in split-drain MOS transistor has been proposed and the susceptibility of these  circuits have been investigated through time domain computer simulations. On the basis of these analyses it has been shown that the new MagFET-based solution (wireless sensing) is more immune to RFI than the wired counterpart.      6 ACKNOWLEDGEMENT The authors wish to thank the Automotive Group of STMicroelectronics that provided the design-kit to perform all the computer analyses. References [1] M. Ramdani, E. Sicard, et al., “The Electromagnetic Compatibility of Integrated Circuits – Past, Present and Future”, IEEE Trans. on EMC, vol.51, no.1, pp. 78-100, Feb. 2009. [2] S. Graffi, G. Masetti, et al., “Criteria to Reduce Failures Induced from Conveyed   Electromagnetic Interferences on CMOS Operational Amplifier”, IEEE Trans. on EMC, vol.51, no.1, pp. 78-100, Feb. 2009. [3] B. Murari, F. Bertotti, Smart power ICs,    Springen, 1995. [4] S. Yuvarajan, L. Wang, “Performance Analysis and signal processing in a current sensing power MOSFET (SENSEFET)”, in Proc. 1990 Industry Applications Society Annual Meeting, vol.2 pp. 1445 – 1450, 28 Sept.-4 Oct. 1991. [5] H. P. Forghani-zadeh, G. A. Rincon-Mora, “Current-sensing techniques for DC-DC converters”, in Proc. 2002 Midwest Symp. on Circuits and Systems (MWSCAS), vol.2 pp. 577–580, 4-7 Aug. 2002.  [6] P. W. Fry, S. J. Hoey, “A Silicon MOS magnetic field transducer of high sensitivity”, IEEE Trans. on Eln Dev., Vol. ED-16, pp. 35-39. 1969. [7] R. S. Popovic, Hall Effect Devices - Second Edition, Institute of Physics Publishing Bristol and Philadelphia, 2004. [8] Jungermann et al., “Correlation factor Studies”, IEEE Trans. on Eln. Dev., Vol.46, n.8, Aug. 1999. [9] www.ansoft.com. [10] F.C. Castaldo, C.A. dos Reis Filho, “Transversal Noise Current: An Excess Noise in CMOS Split-Drain Transistors”, IEEE Trans. on Eln Dev., Volume 54, Issue 4, pp. 885 – 887, April 2007. [11] F. C. Castaldo, V. R. Mognon, C. A. dos Reis Filho, “Magnetical Coupled Current Sensors Using CMOS Split-Drain Transistors”, IEEE Trans. on Power Electron., Volume 24, issue 7, pp. 1733 – 1726, July 2009. [12]IEC 623132-4: Integrated Circuits, Measurement of Electromagnetic Immunity – Part 4: Direct RF Power Injection Method. 

Investigation on the Susceptibility of Integrated Current Sensors to EMI

PORTO Publications Open Repository TOrino

Design of a new MagFET-based Integrated Current 
Sensor Robust to EMI 
 
Orazio Aiello Franco Fiori 
EMC Competence Center Microelectronics EMC Group, 
Istituto Superiore M. Boella (ISMB) Eln. Dpt., Politecnico di Torino, 
Via P. C. Boggio 61, Turin, Italy C.so Duca degli Abruzzi 24, Turin, Italy 
aiello@ismb.it franco.fiori@polito.it 
 
 
Abstract − This paper deals with the susceptibility to 
electromagnetic interference of CMOS integrated 
current sensors for power transistor current 
monitoring. Conventional integrated solution are first 
considered, hence a new integrated current sensor 
based on the Hall effect in a split-drain MOS 
transistors (MagFET) is proposed.  The susceptibility 
to radio frequency interference of a conventional 
(wired) current sensor and that of the MagFET-based 
solution is discussed. 
1 INTRODUCTION 
Common electronic systems are usually made of 
several  modules that include printed circuit boards 
(PCBs), discrete components and integrated circuits 
(ICs). Power and data interconnects in such systems 
are usually routed through cables, which in turn 
behave like unintentional antennas collecting 
electromagnetic interference (EMI) from the 
surrounding environment. 
Although several studies have dealt with the  
susceptibility of integrated circuits to EMI [1-2], such 
a topic is far from being completely addressed and 
deserves further insights. To this purpose, the paper 
introduces the susceptibility to radio frequency 
interference (RFI) of common analog, digital and 
power front-end circuits like those used in 
Application-Specific-Integrated-Circuits (ASICs), then 
it focuses on Smart-Power System-on-Chip [3] and in 
particular on the susceptibility to RFI of conventional 
integrated current sensors needed for power transistor 
current monitoring. 
Common circuits for current sensing use a small 
resistor in series with the power transistor that 
translates the transistor current in a voltage to be 
further amplified and processed. Other current sensing 
circuits base their operation on the current mirroring 
principle: a small transistor (the SenseFET [4-5]) is 
driven by the same gate-source voltage of the power 
transistor so that its drain current is proportional to the 
power transistor current. Such integrated current 
sensors show low-power dissipation, need reduced 
silicon area and provide reasonable accuracy. 
However, any current sensor electrically connected to 
power transistor terminals like those mentioned above, 
is  exposed  to  interference collected by cables. For 
this reason additional passive filters at printed circuit 
board (PCB) or at IC level are usually needed. Based 
on that and aiming at the design of integrated current 
sensors intrinsically immune to EMI, this paper 
describes a new current sensor based on the Hall 
effect, which takes place in a split-drain nMOS 
transistor (the MagFET) whenever it is surrounded by 
the magnetic field of the current to be monitored [6]. 
The paper is organized as follows: Section 2 describes 
a circuit that implements the current mirroring 
principle (the SenseFET circuit). Section 3 recalls how 
magnetic field unbalances the drain current of a 
splitted drain MOS transistor (MagFET) and shows 
the operation of the new current sensor developed in 
this work. Then, Section 4 shows the results of 
computer simulations carried out to evaluate the 
susceptibility of the MagFET-based current sensor. 
These results are compared with those of the 
SenseFET that operates in the same condition. Finally, 
in Section 5 some concluding remarks are drawn. 
 
 
MOS
DRIVER
OV_PROT+
-
POWER MOS
SENSE
FET
ISENSE IXVDD
VSS
 
Fig. 1: Current sensor based on the mirroring principle. 
MAGFET
PAD
Power
Mos

D1
D2
L
W
L
ID2 ID1
MAGFET  
Fig. 2: MagFET symbol and layout view. 
 
0 20 40 60 80 100 120
800
1000
1200
1400
1600
1800
2000
2200
2400
Distance [μm]
B 
[μT
]
 
Fig. 3: Vertical Magnetic Field strength vs distance 
impinging the MagFET. Power transistor current Ix=1A. 
 
2 A CONVENTIONAL CURRENT SENSOR: 
THE SENSEFET CIRCUIT 
A common way of sensing the current that flows 
through a power transistor consists in mirroring it by 
means of a circuit  like  that shown in Fig. 1, where an 
elementary  transistor (the SenseFET) of the same type  
of those used in the power transistor is driven by the 
same gate-source voltage of the power transistor itself. 
The SenseFET drain-source voltage is kept equal  to 
that of the switched-on power transistor by means of a 
voltage follower. Such a bias circuit makes the 
SenseFET drain current (Isense) proportional to that of 
the power transistor (Ix) through a constant mirroring 
factor, which is given by the ratio of the two 
transistors areas (transistors with the same channel 
length are considered). To this purpose, it is worth 
mentioning that the accuracy of such a circuit is surely 
limited by the transistor mismatches, which always 
occurs for high mirroring factor. 
However, the accuracy of such a current sensor can be 
significantly reduced by disturbances affecting the 
power transistor nominal signals and, for this reason, 
the possibility of building up a current sensor with no 
electrical connection with the power transistor 
terminals and limited bandwidth has been investigated. 
To this purpose, the idea of monitoring the power 
transistor current by sensing the magnitude of the 
related magnetic field has been considered. 
3 A NEW CURRENT SENSOR BASED ON 
THE MAGFET TRANSISTOR 
An alternative way of monitoring the power transistor 
current is that of sensing the magnetic field, which is 
related to such a current, through the Hall effect that 
takes place in the channel of a MOS transistor 
surrounded by the magnetic field. To this purpose, 
let’s consider a splitted-drain MOS transistor 
(MagFET) placed very close to a metal strip which 
carries  the current to be monitored, and let’s further  
assume such a sensing transistor biased in saturation. 
In this condition, the power transistor current gives 
rise to the magnetic field that induces a Lorentz force 
on the electrons that flow from the source to the drain 
in MagFET channel: in fact, the split-drain currents 
are imbalanced by the Hall effect. To this purpose, 
previous works [7-8] have   shown   that   the    current  
unbalance  (ΔI) can  be expressed as 
 
                    xcBIBI IFISBISI ==Δ ⊥                  (1) 
 
where IB is the split-drain MOS bias current (ID2+ID1); 
Fc is a conversion factor defined as the ratio of the 
magnetic flux lines density over  the split-drain 
transistor to the current (Ix) flowing through the metal 
strip current. Furthermore, SI is the MagFET 
sensitivity that depends on the geometry of the device 
(length L and width W), and that can be written as  
 
HHchI GW
LS μ
2
1= .  (2)  
 
In this expression, GH is a geometrical correction 
factor (GH=0.676 for square transistor that maximizes 
the sensor sensitivity) and µHch is the Hall carrier 
mobility given by the product of the effective carrier 
mobility µn (process-based) and the Hall factor rH. 
This last factor is almost independent on temperature 
(rH = 1.05 for current sensor operating temperature 
dropping in the range 20°C < T < 120°C  [9]), hence 
current sensing circuits based on MagFET are suitable 
to be embedded in power transistors and smart-power 
system-on-chips that usually experience large 
temperature variations.  
In this work, the conversion factor Fc that relates the 
normal magnetic field strength with the current Ix has 
been evaluated performing electromagnetic 
simulations for a  metal strip of thickness t=4µm and 
width w=10µm [7]. Computer simulations have been 
repeated for several metal-strip-to-MagFET distances 
in the range 0 - 130µm and the results are shown in 
Fig. 3.  On   the  basis   of   these   considerations   and 
VBIAS3
S S
VOUT2
M5
SS
VDD
VOUT1
M8M7
M6
M4
M2M1
M3
M10M9
VBIAS2
MAGFET
VBIAS1
VBIAS3
VBIAS4VBIAS4
VBIAS2
IB
ID1
VBIAS-MAG
ICTRL2 ICTRL1
ID2
 
Fig. 4: Trans-resistance amplifier of the MagFET output 
currents. 
 
referring to a square MagFET (W=L=10µm) and 
metal strip to MagFET distance Δ = 10µm, the 
conversion factor is equal to Fc=1.845mT/A and the 
overall conversion factor is about  ΔI/Ix = 2.5.10-9. 
On the basis of the above mentioned parameters and 
assuming the current to be monitored ranging from 0A 
to 10A, the dynamic range of the MagFET differential 
output current takes values in the range 0-50nA. Being 
this current unbalance so small a trans-resistance high-
gain amplifier  (folded cascade topology) like that 
shown  in  Fig. 4  has  been  designed  referring  to  an  
 
auxiliary circuit for offset cancellation like 0.35µm 
CMOS technology process.  This gain stage shows a 
trans-resistance greater than 100dBΩ and it that 
sketched in Fig. 5. Offset compensation is performed 
whenever the power transistor is switched-off and no 
current flows through the power transistor. In this 
condition, the feedback loop, which is made of a 
voltage comparator, a 10-bit up/down counter, a DAC 
converter and a fully differential trans-conductance 
amplifier (OTA in Fig. 5), forces the sensor 
differential output voltage (VOUT=VOUT2-VOUT1) to zero. 
In particular, with the err_signal set high, the 
comparator output voltage VO_comp  could be high or 
low depending on the offset sign. In the first case (i.e. 
VO_comp  high) the binary counter is enabled to count up 
and the compensation process start taking place, while 
in the second case  (i.e. VO_comp  low) the logic control 
signal (err_signal) is set to zero and the comparator 
input voltage is inverted. Also in this last case the 
binary counter is made counting up. 
The code generated by the binary counter is provided 
to a C-2C DAC that translated it to a voltage hence to 
the current imbalance ICTRL1-ICTRL2. This upset in the 
gain stage bias current compensates the trans-
resistance output offset voltage. This compensation 
proceeds step-by-step as long as the comparator output 
voltage (VO_comp) switches from high to low,  then the 
binary count starts proceeding backward. Once the 
comparator output voltage toggles stably to the clock 
frequency, the compensation process is stopped and 
the resulting binary code, which is proportional to the 
amplifier input offset current, is then  stored in a 
binary register.  This code is constantly used during 
the current sensing for offset compensation purposes. 
Fig. 5: Block diagram of the auxiliary circuit for compensating the trans-resistance amplifier output offset voltage. 
 
10-bit
Counter
up/down
C-2C
DAC
OTA
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
err_sign
err_sign
err_sign
err_sign
err_sign
err_sign
err_sign
err_sign
I-V
gain
Comparator
ck
up/
down
VOUT2 VOUT1
ICTRL2
ICTRL1
VO_comp
VBIAS-MAG
MAGFET
Cbp
Ccore
s
u
b
s
tr
a
te
m
o
d
e
l
p
a
c
k
a
g
e
m
o
d
e
l
CURRENT
SENSOR
VDD
VSS
bias T
+
-
50
VPSVRF
ASIC
power MOS  
 
Fig. 6: Schematic view of the circuit including the current 
sensor, which has been considered for computer simulations. 
RFI is superimposed to the drain voltage using the DPI 
method. 
 
0 5 10 15 20
−80
−60
−40
−20
0
20
40
60
80
Disturbance amplitude [V]
Cu
rre
nt
 se
ns
ed
 e
rro
r (
%)
 
 
max MagFET
min MagFET
avg MagFET
max SenseFET
min SenseFET
avg SenseFET
 
Fig. 7: Maximum, minimum and average value of the 
current-sensed error by MagFET and SenseFET versus 
RFI amplitude. CW interference at 20MHz. 
4 SUSCEPTIBILITY TO RFI OF 
INTEGRATED CURRENT SENSORS 
In this section the susceptibility to RFI of the above 
described current sensors added to the nominal signals 
of a power transistor is investigated. In particular, the 
case of a power transistor integrated in the same 
silicon die with a bunch of analog and digital blocks 
including a current sensor is considered, and it is 
assumed that all signal circuits share the same power 
supply rails. Analyses have been carried out referring 
to the schematic view of Fig. 6 that includes a 2 mm2 
power transistor, the substrate parasitic model, the 
package parasitic model and the schematic view of the 
current sensor under analysis. Furthermore, all circuits 
of the SoC except the power transistor and the current 
0 1 2 3 4 5 6
−100
−80
−60
−40
−20
0
20
40
Disturbance amplitude [V]
Cu
rre
nt
 se
ns
ed
 e
rro
r (
%)
 
 
max MagFET
min MagFET
avg MagFET
max SenseFET
min SenseFET
avg SenseFET
 
Fig. 8: Maximum, minimum and average value of the 
current-sensed error by MagFET and SenseFET versus 
RFI amplitude. CW interference at 100MHz. 
 
0 2 4 6 8 10 12
−250
−200
−150
−100
−50
0
50
100
Disturbance amplitude [V]
Cu
rre
nt
 se
ns
ed
 e
rro
r (
%)
 
 
max MagFET
min MagFET
avg MagFET
max SenseFET
min SenseFET
avg SenseFET
 
Fig. 9: Maximum, minimum and average value of the 
current-sensed error by MagFET and SenseFET versus 
RFI amplitude. CW interference at 200MHz. 
 
sensor have been roughly modeled by an on-chip 
capacitance connected to the power supply and ground 
rails. Simulations have been carried out with the 
power transistor switched-on and the RFI added to the 
drain terminal using the direct power injection method 
[12]. In this framework, time domain simulations were 
performed using ELDO (a SPICE-like simulator) and 
the RFI-induced upset of the current sensor output 
signal (Isense in the SenseFET circuit and the output 
voltage VOUT of the MagFET trans-resistance 
amplifier) has been recorded. These simulation results 
are shown in Figs. 7, 8, 9 where the minimum, 
maximum and average value of the output signal RFI-
induced upset versus RFI amplitude is reported. In 
particular, Figs. 7, 8, 9 have been obtained considering 
CW interference at 20MHz, 100MHz, 200MHz 
respectively. With reference to these results it can be 
concluded that the  immunity  of   the    MagFET-
based current sensor (wireless sensor)  is  significantly 
106 107 108 109
−140
−120
−100
−80
−60
−40
−20
0
[d
B V
]
Frequency [Hz]
 
 
VDD
Drain
 
 
Fig. 10: AC analysis: RFI magnitude resulting at the 
switched-on power MOS drain terminal and at the current 
sensor power supply (VDD) referred to VSS. 
 
greater than that of the SenseFET (wired sensor). 
However, it should be also noticed that both current 
sensors are more susceptibility to RFI in the frequency 
range around 100MHz. To this purpose, further 
analyses based on small-signal computer simulations 
have shown that RFI added to the power transistor 
drives the parallel resonance of the power supply 
package parasitic inductances (VDD-VSS) and the on-
chip parasitic capacitance CCORE (see Fig. 6). 
Around this resonance (about 100MHz in the circuit 
under analysis) the amplitude of RFI that results added 
to the current sensor power-supply voltage takes 
magnitude comparable with that at the power 
transistor drain terminal, as it is highlighted by the 
plots in Fig. 10. 
 
 
5 CONCLUSION 
In this work, the susceptibility to RFI of integrated 
sensors for power transistor current monitoring has 
been discussed. To this purpose, a conventional 
current sensor, which is electrically connected by 
metal strips to the power transistor terminals, has been 
considered. Furthermore, a new wireless current 
sensor, which is based on the Hall effect in split-drain 
MOS transistor has been proposed and the 
susceptibility of these  circuits have been investigated 
through time domain computer simulations. On the 
basis of these analyses it has been shown that the new 
MagFET-based solution (wireless sensing) is more 
immune to RFI than the wired counterpart. 
 
 
 
 
 
6 ACKNOWLEDGEMENT 
The authors wish to thank the Automotive Group of 
STMicroelectronics that provided the design-kit to 
perform all the computer analyses. 
References 
[1] M. Ramdani, E. Sicard, et al., “The 
Electromagnetic Compatibility of Integrated 
Circuits – Past, Present and Future”, IEEE Trans. 
on EMC, vol.51, no.1, pp. 78-100, Feb. 2009. 
[2] S. Graffi, G. Masetti, et al., “Criteria to Reduce 
Failures Induced from Conveyed   
Electromagnetic Interferences on CMOS 
Operational Amplifier”, IEEE Trans. on EMC, 
vol.51, no.1, pp. 78-100, Feb. 2009. 
[3] B. Murari, F. Bertotti, Smart power ICs,    
Springen, 1995. 
[4] S. Yuvarajan, L. Wang, “Performance Analysis 
and signal processing in a current sensing power 
MOSFET (SENSEFET)”, in Proc. 1990 Industry 
Applications Society Annual Meeting, vol.2 pp. 
1445 – 1450, 28 Sept.-4 Oct. 1991. 
[5] H. P. Forghani-zadeh, G. A. Rincon-Mora, 
“Current-sensing techniques for DC-DC 
converters”, in Proc. 2002 Midwest Symp. on 
Circuits and Systems (MWSCAS), vol.2 pp. 577–
580, 4-7 Aug. 2002. 
 [6] P. W. Fry, S. J. Hoey, “A Silicon MOS magnetic 
field transducer of high sensitivity”, IEEE Trans. 
on Eln Dev., Vol. ED-16, pp. 35-39. 1969. 
[7] R. S. Popovic, Hall Effect Devices - Second 
Edition, Institute of Physics Publishing Bristol 
and Philadelphia, 2004. 
[8] Jungermann et al., “Correlation factor Studies”, 
IEEE Trans. on Eln. Dev., Vol.46, n.8, Aug. 
1999. 
[9] www.ansoft.com. 
[10] F.C. Castaldo, C.A. dos Reis Filho, 
“Transversal Noise Current: An Excess Noise in 
CMOS Split-Drain Transistors”, IEEE Trans. on 
Eln Dev., Volume 54, Issue 4, pp. 885 – 887, 
April 2007. 
[11] F. C. Castaldo, V. R. Mognon, C. A. dos Reis 
Filho, “Magnetical Coupled Current Sensors 
Using CMOS Split-Drain Transistors”, IEEE 
Trans. on Power Electron., Volume 24, issue 7, 
pp. 1733 – 1726, July 2009. 
[12]IEC 623132-4: Integrated Circuits, Measurement 
of Electromagnetic Immunity – Part 4: Direct RF 
Power Injection Method. 


A Silicon MOS magnetic field transducer of high sensitivity”,

Correlation factor Studies”,

Criteria to Reduce Failures Induced from Conveyed Electromagnetic Interferences

Current-sensing techniques for DC-DC converters”, in

dos Reis Filho, “Magnetical Coupled Current Sensors Using CMOS Split-Drain Transistors”,

dos Reis Filho, “Transversal Noise Current: An Excess Noise in CMOS Split-Drain Transistors”,

Hall Effect Devices - Second Edition,

Integrated Circuits,

Performance Analysis and signal processing in a current sensing power MOSFET (SENSEFET)”, in

Smart power ICs,

The Electromagnetic Compatibility of Integrated Circuits – Past, Present and Future”,

https://iris.polito.it/retrieve/handle/11583/2291474/51958/lv_EMC_compo09_05102009%20_3_.pdf

Investigation on the Susceptibility of Integrated Current Sensors to EMI

Abstract

Similar works

Full text

Available Versions

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

PORTO Publications Open Repository TOrino