Asynchronous digital interface circuits exhibit a high degree of concurrency. Self-timed implementation is the most appropriate design discipline for such circuits. Their complexity demands that a formal design methodology, amenable to automation, is used to design them. Existing specification models suffer from severe limitations when it comes to describing the circuit function at a high level, which requires decomposing the specification into intercommunicating sub-modules and synthesizing a logic circuit implementation of that function. We propose a new methodology to design asynchronous circuits that is divided in two stages: abstract synthesis and logic synthesis. The first stage is carried out by refining an abstract model, based on logic predicates describing the correct input-output behavior of the circuit, into a labeled Petri net and then into a formalization of timing diagrams (the Signal Transition Graph). This refinement involves hierarchical decomposition of the initial i..
