Supply Current Testing (IDDQ) has become an important defect oriented test strategy for digital IC products. The technique takes advantage of the low quiescent supply current drawn by static CMOS circuits relative to the current consumption during state changes. However, in analogue and mixed signal IC’s this condition can rarely be observed, as in most circuits, steady state currents depend on the biasing conditions and the circuit design. This paper reviews analogue current monitoring proposals, investigates some of the problems related to the use of these techniques and attempts to categorise a number of analogue design styles against the probable suitability for current testing methodologies

Baturone, I

Bratt, Adrian

HUERTAS, J L

Richardson, Andrew

English

Lancaster E-Prints

Mixed Signal Test Workshop 1 Grenoble 1995The Application of IDDX Test Strategies in Analogue andMixed Signal IC’sAdrian Bratt1, Andrew Richardson1, Iluminada Baturone2 & Jose Luis Huertas2AbstractSupply Current Testing (IDDQ) has become an important defect oriented teststrategy for digital IC products. The technique takes advantage of the lowquiescent supply current drawn by static CMOS circuits relative to thecurrent consumption during state changes. However, in analogue andmixed signal IC’s this condition can rarely be observed, as in most circuits,steady state currents depend on the biasing conditions and the circuitdesign.This paper reviews analogue current monitoring proposals, investigatessome of the problems related to the use of these techniques and attempts tocategorise a number of analogue design styles against the probablesuitability for current testing methodologies.1 IntroductionIn the digital world, supply current monitoringis almost entirely based on IDDQ testing thatinvolves measurements of supply current in thequiescent state. For analogue circuits, severalschemes exist and are generically referred to asIDDX where, (amongst others) the "x" may be a"d"  to represent dynamic current measurement,a "q" to represent static current measurement ora “t” to represent transient currentmeasurement. This paper aims to summariseproposals for current monitoring and discussesthe effect of process variations on fault freequiescent current levels. An initial study intoanalogue circuit design styles and the predictedeffectiveness of current testing for a number ofexamples extracted from a categorisationprocess will be reported.2. Current Monitoring TechniquesA number of supply current monitoringtechniques for testing analogue and mixedsignal IC’s have been proposed [1-6] that havegenerated results that in many cases arecontradictory. In [1] IDDQ levels for both opensand shorts in a Sallen and Key high pass filterwere investigated. Results showed that DCvoltage measurements were far more effective.On the other hand simulation results obtainedon a op-amp structure [2] identified 80% ofsimulated defects causing supply currentchanges of >25%. In this study, DC sweeps ofthe input voltages was found to be the mostrevealing test vectors. A continuation of this1Engineering Department 2CNM Lancaster University Avda.Reina Mercedes s/n Lancaster, LA1 4YR Universidad de Sevilla UK. 41012 Sevilla (Spain)Mixed Signal Test Workshop 2 Grenoble 1995work led to the use of non-periodic pseudorandom signals being used as input vectors [3].Steady state response magnitudes such asRMS. values are extracted from the supplycurrent in [4] for various analogue circuitsexercised by sinusoidal or square wave inputs.Optimisation of  input conditions have beenshown to generate high fault coverages. Theapproach of transient response IDDT has beenused on continuous time filters in [5]. This ishowever more complex requiring built-in-self-test (BIST) circuitry. Initial results have againsuggested high coverage. Pulse response testinghas been suggested in [6]. In this case the VDDand VSS rails are pulsed whilst applying a fixedvoltage on the inputs. Temporal and spectralanalysis is then applied to the transient railcurrent.3. Effect of Process VariationsIn the majority of previous studies, the effect ofprocess variations on fault free current levelshas been identified as being critical for bothsetting pass/fail thresholds and derivingrealistic coverage figures. The following sectionsummarises an evaluation carried out on thecurrent reference cell shown in fig 1 andsubsequent measurements on silicon. [7]. Inthis circuit the reference current is given by:IrefV QREB= ( )11           (1)Both absolute and relative component variationhas been evaluated across a single wafer andfrom wafer to wafer for both biasing and biasedcells.3.1 Absolute Component VariationThe reference current generated in the circuitshown in fig. 1 is dependent on the emitter-basevoltage drop of transistor Q1(VBE) and thevalue of resistor R1. The value of (VBE)Q1 doesnot vary significantly in relation to the processdependent value of the resistor R1 which doesshow considerable  variation. The minimum,typical and maximum process values( i . e . ± 3 σ )  for resistor R1 have beenconsidered to evaluate the range of currentvariations. A hand calculation of current rangeand a 1000 point monte-carlo simulation, usingthe same parameters, gives the results shown infig. 2.The balanced nature of this current sourceensures that absolute component variation ofthe MOS transistors has only a relatively smalleffect on the reference current value.  A 1000point monte-carlo simulation of the MOSHSPICE parameters, within 3σ  limits, yields acurrent variability 3σ  value of only 0.24μA.Temperature variation affects the referencecurrent value in that both the value of resistorR1 and VBE(Q1) are temperature dependent.Respective temperature coefficients aretypically +3600ppm/oC  and -2mV/oC whichgives a net temperature coefficient of -0.3μA/oC for the whole circuit. Assuming thetesting temperature can be controlled to within30uA 40uA 50uA 60uAMCHandFigure 1: Schematic of current reference cell (iref)P1N1Q1VddP2N2R1P3VssIrefFigure 2: Hand & Monte-carlo 3σ  simulationresultsMixed Signal Test Workshop 3 Grenoble 1995a range of ± 5oC then the total current changedue to this effect is ± 1.5μA.The absolute value of resistor R1 dominatesother absolute value sources of currentvariability. A superposition of the effects ofvariation of resistor value, FET process valuesand temperature variation is illustrated in Fig.3.3.2 Relative component variationRelative component variation (mismatch)manifests itself as two problems. First,mismatches within the components of the twoarms of the current reference cell shown in fig.1 cause small changes in the value of thereference current.  Second, two or more currentreference cells will not carry exactly the samecurrent since their resistor values will alsogenerally not be equal.3.2.1 Relative component variation withinone cellIdeally, the transistor pairs P1,P2 and N1,N2are perfectly matched to ensure that thecurrents in either arm of the reference cell areequal.  Using process mismatch data anaccurate estimate of the maximum likelycurrent mismatch may be obtained by handcalculation.  If the input referred thresholdvoltage (VT) mismatch (the net effect of bothVT and all other process parametermismatches) is defined to be Δ VT  for bothNMOS andPMOS devices the necessary changes to theMOS transistors of fig. 1 to generate maximumcurrent offset within the core are those shownin Fig.4. The sense of VT changes does notmatter since the results are combined inquadrature.The drain-source current of a MOS transistoroperating in the saturation region may bewritten to a good approximation as,( )I K WLV VDO GS T= −122                    (2)where K 1  is the MOS transconductanceparameter, W and L are the width and length ofthe MOS transistor respectively, VGS is thegate-source voltage and VT is the thresholdvoltage. If the change in the value of VT(Δ VT) is small with respect to its nominalvalue the equation representing the current withoffset values present is written,I D = K 1 W 2 L V GS − V T + Δ V T ( ) 2 .                 (3)and the change in current may be approximatedto:Δ I D = K 1 W P L P V GSP − V T P ( ) Δ V T P                 (4)where Δ ID is the change in drain current andall other symbols have the same meaning as ineq. 2.  In the reference cell shown in fig. 1 thenet mismatch in currents between transistors P1and P2 is thus,N1 N2 P2 P3P10+ΔVt-ΔVt|Vt|3.5 4.0 4.5 5.0 5.5 6.00504030201060+5C-5C×10-5Current (A)NumberFigure 3: Resistor, FET parameter andtemperature effects on reference currentFigure 4: Parameter changes necessary formaximal current offsetMixed Signal Test Workshop 4 Grenoble 1995Δ I P 12 = K 1 W L V GS − V T ( ) Δ V T .                 (5)The threshold voltage mismatch of N1 and N2causes the voltage drop on the resistor Rq tochange by Δ V T .(It has been assumed that thesmall current mismatch between transistors N1and N2 has negligible effect on mismatchingtheir gate-source voltages.)  Mismatch betweentransistors P2 and P3 must also be accountedfor usingΔ I P 23 = K 1 W P 3 L P 3 V GS − V T ( ) Δ V T 3              (6)where A3 is the aspect ratio of transistor P3and  Δ V T 3  is its threshold voltage shift fromthe nominal value of VT.Inserting the 3σ  values for Δ V T  intoequations 4,5 and 6 are combining them inquadrature (i.e. assuming no correlationbetween offset values and taking into accountthat P2 and P3 act so as to reduce the RMScore current error by a factor of 8 / 1218 / 10 ) givesa predicted 3σ  current mismatch of 0.22μA.A monte-carlo simulation of the same circuitwith the same offset values gives a 3σ currenttolerance of 0.32μA.  Hand calculation andmonte-carlo results are shown in fig. 5.3.2.2 Relative component variationbetween cellsIn addition to the current tolerance predicted inthe above section there will also be an intracellular current tolerance caused by resistormismatch.  This may be calculated in the sameway as for the wafer current distribution butusing the resistor matching value rather thanthe absolute resistor value range.  A value of± 0.46μ A is predicted for this component ofthe 3σ  current variation assuming a 1%resistor match from cell to cell.Combining in quadrature this current variationvalue with that shown in fig. 5 the net currentvariation is ± 0.6μΑ about the nominal currentat the ± 3σ  level.4 Measured results4.1 Test chipFigure 6 shows a schematic diagram of a testchip which was fabricated to test the accuracyof the predicted current variation values.  Thechip consists of five current reference cells eachidentical to that shown in fig. 1.  One of thesereference cells was used to generate a biascurrent for five operational amplifiers.  Tenchips were fabricated in total.4.2 Fully on chip reference circuitThe average current drawn by all the currentreference cells will give an indication of theaccuracy of the prediction of absolute currentvalue determined primarily by the value of thebias resistor, R1.  The average measured valueof reference current was 18.77μA measuredover all current reference cells on all chips.Figure 7 compares this with the hand calculatedand monte-carlo calculated results.  Ideallyseveral wafers from different batches should be16uA 17uA 18uAMCHandFigure 5: Hand and monte-carlo 3 offsetsimulation results-+-+-+-+-+- nodes pinned outFigure 6: Schematic diagram of current referencechip cellsMixed Signal Test Workshop 5 Grenoble 1995used to verify this prediction, but cost and  timescale constraints made this impractical.  Withinthese limitations the measured results areconsistent with those predicted.4.3 Relative component variation  effectsMeasurement of the scatter on the currentdrawn by the five reference cells on one chipallows the total mismatch induced currentscatter component to be determined.  Theaverage scatter of current values measured inthis way over all chips at the ± 3σ  level is0.81μA in 18.77μA. Comparing this value withpredicted scatter values of ± 0.6μA for handcalculation and ± 0.86μA for monte-carlosimulation.  We can conclude that agreementbetween monte-carlo simulation and silicon isthus good although  hand calculations are lessaccurate.4.4 Fully off chip current sourceAll five operational amplifiers on one chip arebiased from one current source, thus scatter ofIddq current values among these fiveoperational amplifiers gives a measure of theaccuracy  of Iddq current which could beobtained from the use of a fully off chipreference circuit. The average measured scatter(at 3σ  level) over all ten chips was 7.2μ A in134.8μ A which amounts to approximately 5%.5 Normal IDD distributionsWe can now conclude that absolute componentvariation has been shown to be the major causeof variation of current reference value on astandard CMOS process if a fully on-chipreference cell is used.  If  one (or more)components are taken off chip to improveaccuracy then mismatch between componentson chip has been shown to determine theaccuracy by which an IDDQ current can bedetermined.For the fabrication process used by the authors,an approximate IDDQ current definitionaccuracy of 5μ A exists.  However, in manycases the transistors N1,N2 and P1,P2  in fig 1will not be physically close and the netthreshold voltage offset between them will belarger than those used in this paper.Temperature gradients across a chip will alsobecome an important issue in this situation.Poorer definition of the IDDQ current will resultand an IDDQ current definition error in excess of5μ A will be observed.6. Potential applications of IDDXIt is likely that future applications of supplycurrent monitoring will need to address theabove problems as well as the relatively highquiescent current levels in many analoguecircuits. In analogue design there is often atrade off between high speed operation and lowpower dissipation causing supply currents tovary between zero to several mA from design todesign. Another point worth considering is theinfluence of the input signals. In most digitalcircuits, the inputs do not have a significanteffect on supply current levels. This is not thecase in many analogue designs. In an attempt toformalise the applicability of IDDX techniques,three dominant design styles have beenidentified.6.1 1. High IDDThis tends to be a consequence of class Abehavior of many circuits in which the outputcurrent can never exceed the bias current. Sincethe bias current is constant, either IDDQ or ISSQare independent of the input signals. Somecircuits which belong to this group areconventional two stage voltage modecomparators and amplifiers, one stage (folded-cascode) amplifiers or current mode blockssuch as class A switched current memory cells.12uA 17uA 22uAMCHand19.5uA14.5uASilicon average resultFigure 7: Measured average and hand andmonte-carlo 3σ current valuesMixed Signal Test Workshop 6 Grenoble 19956.2 IDD  a function of inputsThese circuits are designed to consume a lowquiescent current whilst maintaining a highdriving capability. They can source or sinkcurrent from a load which is greater than thebias current. This extra current is provided bythe power supplies, either directly as is the casein class AB circuits (buffers, currentconveyors, class AB memory cells etc) or via adynamic or input dependent current source(dynamic and adaptive biasing amplifiers).6.3  Low IDDThese tend to be circuits that are driven by theirinputs so that in the absence of input signalstheir quiescent current is practically zero.These circuits result from the combination ofcurrent mirrors without biasing currents, suchas current mode maximum operators, currentmode full wave rectifiers and some currentmode A-D and D-A converters.An intuitive analysis suggests that supplycurrent testing will be more applicable to thelatter two categories of circuits. A collaborativeproject between Lancaster University and CNMis in progress which involves an analysis of theeffectiveness of IDDX techniques for specificexamples of circuits from each of the abovecategories. This will involve the application ofresults presented in section 3 to determinerealistic pass/fail thresholds and the use ofsensitivity analysis and IFA techniques todetermine the effect of layout dependent defectson various supply current related parameters.7. ConclusionsThis paper has summarised a number of IDDXtechniques for analogue and mixed signalcircuits and reported on results obtained fromthe evaluation of  the effect of processvariations on fault free quiescent current levels.It has been shown that the distribution of faultfree quiescent current levels will be greater than+/-5% and that in most applications, especiallywhere on chip reference current generation isused a pass/fail threshold of at least +/-20%should be used.An initial attempt has also been made tocategorise analogue circuits against supplycurrent behavior with the aim of determiningwhich circuit classes will be suitable for IDDXtechniques to be used.8. References[1] R.J.Harvey, A.H.Bratt, & A.P.Dorey"A review of testing methods for mixed signal ICs" Microelectronics Journal, vol 24, no 6, pp 663-674, Oct 1993.[2] Bell I.M. et al.: "Supply Current Testing ofMixed Analogue & Digital ICs".  ElectronicsLett. Vol 27. pp1581-1583[3] Eckersall K.R. et al.: "Testing Mixed SignalASICs Through The Use of Supply CurrentMonitoring".  ETC. 1993 pp385-391[4] Suparjo B.S & Wilkins B.R “TestingAnalogue & Mixed Signal Modules by Steady-State Response Monitoring” Internal Report1995.[5] Arguelles J, Lopez M, Blanco, J & MartinezM “IDDt testing of continuous time filters”VLSI Test Symposium, May 1995.[6] Beasley J, Ramamurthy H, Ramirez-Angulo J& Deyong M. “IDD Pulse Response Testing ofAnalogue & Digital CMOS Circuits” ITC1993.[7] A H Bratt, R.J Harvey, A.P Dorey & A M Richardson "Aspects of Current Reference Generation and Distribution for IDDx Pass/Fail Current Determination" IEE Colloquium on Mixed Signal VLSI Test, London 13th Dec 1993. Digest no 1993/240, pp3/1-3/8.

Distribution for IDDx Pass/Fail Current Determination&quot;

The application of IDDX test strategies in analogue and mixed signal IC's

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The application of IDDX test strategies in analogue and mixed signal IC's

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