Approximate and error tolerant circuits are a radical new approach to trade calculation accuracy for better speed, power, area and yield. The IcySoC project platform revisits low-power and low-voltage VLSI design through a cross-layer combined inexact design framework

Burg, Andreas Peter

Camus, Vincent

Enz, Christian

Karakonstantis, Georgios

Schlachter, Jérémy

Infoscience - École polytechnique fédérale de Lausanne

Example of K-Maps of the (a) initial Correct Function (carry of a full adder)(b) function with a favorable 0 to 1 bit flip (c) function with a favorable 1 to 0 bit flip (d) function with a non-favorable 0 to 1 bit flip [2]Cross-Layer Inexact Design for Low-Power ApplicationsIcySoC RTD 20131 Ecole polytechnique fédérale de Lausanne (EPFL), Integrated Circuits Laboratory (ICLAB)V. Camus1, G. Karakonstantis2, J. Schlachter1, A. Burg2, C. Enz12 Ecole polytechnique fédérale de Lausanne (EPFL), Telecommunications Circuits Lab (TCL)Inexact characterization and co-design frameworkCircuit pruning and minimization Algorithmic pruningCircuit level implementationsAbstractAchieving miniaturization, low-power and real-time data processing requires always more expensive design constraints and margins. Guardbands and worst case safety margins coupled with error correction units to ensure perfect calculations and robustness against Process-Voltage-Temperature (PVT) variations strongly deteriorate chip performance, power and cost efficiency.Approximate and error tolerant circuits are a radical new approach to trade calculation accuracy for better speed, power, area and yield.The IcySoC project platform revisits low-power and low-voltage VLSI design through a cross-layer combined inexact design framework.AlgorithmCircuitDeviceAlgorithmic pruningVoltage-frequency scalingThe main idea in working at circuit level is to conceivefundamentally different circuit schemes to better control thecalculation error characteristics and allow more efficient pruningand minimization of these circuits.Pruning consists in deleting circuit’s gates or cells having the lowestSignificance-Activity Product (SAP).Ranking Scheme for a 16 bits Kogge-Stone adder [1] Gains up to 8X in energy-delay-area product [1]Minimization consists in introducing bit flips in Karnaugh maps oflogic functions in order to reduce circuit complexity.Gains up to 8X in energy-delay-area product [2][1] A. Lingamneni et al., Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling, CF, 2012.[2] A. Lingamneni et al., Parsimonious circuits for error-tolerant applications through probabilistic logic minimization, PATMOS, 2011.[3] M. Weber et al., Balancing Adder for error tolerant applications, ISCAS, 2013.[4] N. Zhu et al., An enhanced low-power high-speed Adder For Error-Tolerant application, ISIC, 2009.16-bit Ripple Carry AdderApproximate speculative adder ETBA: carry speculations atdifferent levels prevent long propagations of carry propagates [3]Quality and Energy-Delay product of JPEG decompression using different speculative adders (ETBA and ETAIIM [4]) versus Kogge-StoneAdder (KSA) and reduced bandwidth Ripple Carry Adder (RBD) [3] Inexact design techniques used independently at anylevel of the system has been proved to lead tosignificant gains in energy efficiency. However, fullyexploiting the potential of these techniques requirescross-level work to adapt to the desired application.By joining forces in a bottom-up approach, two labs atEPFL collaborate in this project, combining theirrespective inexact design methodologies to a holisticframework for low-power design.TCLCircuit level implementationsCircuit pruning and minimization ICLABICLABTCLApplicationVariable robustness memory TCLApproximate algorithmEnergy, delay, areaError characteristicsOptimized applicationInexactbuilding&charac.platformICLAB&TCLPruning at the algorithm level consists of classifying the significanceof computations and skipping the less-significant ones for adjusting todynamically changing hardware capabilities and for saving power. Quality-loss does not affect the ability ofdetecting any sinus arrhythmia condition [5] Many other applications [6, 7]Design for Graceful Quality DegradationGuaranteed Correctness Best- Effort  Computing  - HIGH priority- Time redundancy - Might incur timing penalty- LOW priority- Can be pruned to compensatefor any penalty/facilitate VSInput DataQuality MetricSignificance CharacterizationSignificantComputations  Less-SignificantComputations  Improve CharacteristicsFind a domain in which the input signal is approximately-sparseNoSufficient?YesClassify computations into groups based  on their significance in obtaining adequate Quality xFy = F(x)AlgorithmExpress the signal in such a  domain xWy = G(W(x))Gx’MinorQuality lossEnsure Adequate QualityDWT based FFT  – drop 60% operations LFP/HFP  =  0.4652Conventional FFT (split-radix) LFP/HFP  =  0.451Total LFP = 148.5Total HFP = 319.2Total ULFP= 54.1Total LFP= 151.9Total HFP= 336.8Total ULFP=54.9(Sinus Arrhythmia: dominant HFP in 0.15-0.4 Hz )LF     HF     ULF Application to FFT and Spectral Analysis of Heart Rate[5]  G. Karakonstantis et al., A Quality-Scalable Spectral Analysis System for Energy- Efficient Health Monitoring, DATE, 2014.[6]  G. Karakonstantis et al., Process-Variation Resilient & Voltage-Scalable DCT Architecture for Robust Low-Power Computing, IEEE Trans. on VLSI Systems, 2010.[7]  G. Karakonstantis et al., On the Exploitation of the Error Resilience of Wireless Systems under Unreliable Silicon, DAC, 2012.8-point DWT4-point DWT4-point DWT2-point DWT2-point DWT2-point DWT2-point DWTDWT stage (HF band pruned) Twiddle factors(small factors pruned)

Cross-Layer Inexact Design for Low-Power Applications

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Cross-Layer Inexact Design for Low-Power Applications

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