'Institute of Electrical and Electronics Engineers (IEEE)'
Doi
Abstract
This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference. The proposal was validated using realistic behavioral models and transistor-level simulations in a 0.18μm CMOS technology. The application of the method reduces by several orders of magnitude the number of cycles needed to characterize the offset during design, drastically improving productivity.Junta de Andalucía P09-TIC-5386Ministerio de Economía y Competitividad TEC2011-2830
