The design and performance of a dynamic frequency divider was presented. This digital IC demonstrates the ability of the authors' AlGaAs/GaAs/AlGaAs quantum-well FETs with gate lengths of 0.2 &#956;m. Stable operation was achieved in the frequency range from 18 GHz up to 34 GHz with a power consumption of 250 mW. To the authors' knowledge, this is the best result ever reported for HEMT circuits, and is similar to the frequency limit achieved by use of AlGaAs/GaAs HBTs

Berroth, Manfred

Bosch, Roland

Köhler, Klaus

Nowotny, Ulrich

Raynor, Brian

Schneider, Joachim

Seibel, Jörg

Thiede, Andreas

Online Publikationen der Universität Stuttgart

IEEE JOURNAL OF SOLID·STAT'E CIRCUITS. VOL 28. NO. II. NOVEMBER 1993 1167 
Special Brief Paper _____ ______ _ 
An 18-34-GHz Dynamic Frequency Divider Based on 
0.2-J.Lm AIGaAs/GaAs/AIGaAs Quantum-Well Transistors 
Andreas Thiede, Manfred Berroth, Member, IEEE, Ulrich Nowotny, Jorg 
Seibel, Roland Bosch, Klaus Kohler, Brian Raynor, and Joachim Schneider 
I. INTROOUCTION 
D IGITAL frequency dividers are of increasing importance in a wide field of device applications for high-speed 
communication systems and high-end measuring equipment. 
Ever-increasing frequency limits have led to the demand for 
GaAs approaches. 
Dynamic frequency dividers based on 0.2-J.!m GaAs MES-
FET's have achieved a 26.5-GHz operational frequency [1]. 
Operation also at 26.5 GHz was reponed based on 0.25-
J.!Tn inverted AIGaAs HEMT technology [2], [3]. High-speed 
ECL static frequency dividers using Si bipolar transistors, 
AIGaAs/GaAs hetero bipolar transistors, and AllnAs/InGaAs 
HBT's have achieved operation at 25 GHz, 34.8 GHz, and 
39.5 G Hz. respectively [4)-{6]. 
A promising technology for AlGaAs/GaAs/AlGaAs quan 
tum-well transistors with double-delta doped supply layers 
[7) and gate lengths down to 0.2 JlTn [8) was developed at 
our institute, for high-speed logic [9], [I 0], analog circuits 
[II], and optoelectronic lC's I l2]. An integration complexity 
of 20000 transistors was demonstrated [13]. The design and 
performance of a dynamic frequency divider operating in the 
18-34 GHz range will be presented here. 
II. E/D·ALGAAs/GAAs/ALGAAs 
QUANTUM·WBLL TRANSISTOR PROCESS 
Fig. I shows a cross section of our recessed gate Al-
GaAs/GaAs/AIGaAs double-heterojunction depletion and en-
hancement type transistors with double delta doped supply 
layers. The narrow bandgap GaAs channel forms a quantum 
well between the wide-gap AIGaAs layers. 1be AlGaAs spac-
ers are optimized for high electron transfer from the supply 
layers into the channel, and on the other hand for reduced 
Coulomb scattering by spatial separation of the electrons in 
the channel and donors in the supply Layers. 
AIGaAs etch stops are used for both the enhancement and 
depletion type transistors. The GaAs is removed by a dry etch 
Manuscripl received May 18, 1993; rev~ August 10. 1993. This won.: 
was supported by the German Federal Minisuy of Research and Technology 
under OFE Project TIOS7/8. 
The aulhor$ are with the Fraunhofet' Institute for Applied Solid-State 
Physics. D-79108 Freiburg. Germany. 
IEEE Log Number 9212553. 
E-FET D-FET 
CONTACT 
ot LAYER JOnm ~~ ETCH STCP 3 nm 7Snm a:~ ETCH SliP 3 nm 
6nm 
l J,Jnm 1.7nm 
~~ 3.3nm 2DEG 1Snm N~ 5nm 11 nm 
! 200nm 
"' 
SlPERATla 
t::' 
~ 300,.., Go As 
Fig. I. Cross section of the AIOaAsiGaAs/AIGaAs helerojunclion structute. 
VDD VDD 
OUT 
VSS 
r 
lN 
Fig. 2. Dynamic frequency divider circuit schematic. 
process; the AlGaAs etch stops, however, are removed by 
conventional we& etching. 
This structure offers three advantages over standard MES-
FET's: 
• large carrier density in the channel, typically 1.8 x 1012 
em- 2, and a high electron mobility of about 7000 cm2 N s; 
• high differential drain resistance of about 50 k!l J.ITll, and 
transconductance of about 400 mS/mm due to electron 
confinement in the channel; and 
0018-9200193$03.00 @ 1993 IEEE 
1168 IEEE JOURNAL Of SOUD-STATE CIRCUITS. VOL. 28. NO. I I, NOVEMBER 1993 
VDD VDD VDD VDD 
VSS VSS 
IN VDD VDD VDD VDD 
VSS VSS 
fig. 3. Circuit sc.bematlc of the dynamic frequency divider with a memory type flip-llop. 
TABLE I 
QUAt11VM-WELL TRANSisTOR PARAMETERS FOR 0.2-pM 0A1C LENC'Ilf 
Type 
E 
0 
9m 
> i;OO mS/mm 
> 350 mS/mm 
fr 
> 70 GH.z 
>55OHz 
/mu 
> 100 GH.z 
> 100 GHz 
• precise conrrol of threshold voltage (10 mY standard 
deviation across a 2-in wafer). 
We have developed a mix-and-match techn(!logy combining 
an e-beam with optical lithography whereby thee-beam is used 
for Wfiting the gates only. 
Table I gives an overview of the transconductance 9m, 
the b'ansient frequency h, and the maximum frequency 
I max of our enhancement and depletion type rransistors for 
a gate length of 0.2 J1m. Our standard process sequence 
includes Schottky diodes, NiCr thin-film resistors, and MIM 
capacitors. For optoelecrronic circuits, MSM photodiodes can 
be monolithically integrated [12). Two gold layers are used for 
interconnections, the top layer using an airbridge technique, 
thus reducing parasitic capacitances. 
Ill. CIRCUIT DESIGN 
The maximum input frequency to a static divider is re-
stricted to about 
ltogg = l/2tpd 
where tpd is the delay time of the logic inverter. Dynamic 
frequency dividers generally can operate up to twice the input 
frequelllcy of static dividers: 
ltogg = 1/tpd· 
The simplest realization of a dynamic frequency divider 
is shown in Fig. 2. A single inverter and a buffer stage are 
connected in series, and the output of the buffer is fed back to 
the inverter input by a transfer gate. The inverter is switched 
with h~lf the frequency of the transfer gate. The time at which 
the rransfer gate is switched on due to the high level applied 
to the input is no longer than the delay of the inverter buffer 
chain, and that delay in tum will be shorter than one input 
pulse period. These equations give the upper and lower limits 
of stable operation of the divider circuit 
(2tiNv + 2tSF )- 1 < I < (tJNv + tsp ) - 1 
where tiNv and tsp are the propagation delays of the inverter 
and the source follower, respectively. 
During the time when the transfe.r gate is switched off, the 
logic state is stored only in the capacitance of the high-ohmic 
inverter input node. For higher frequencies, however, espe-
cially for very short rise and fall times, the gate capacitance 
of the transfer gate can cause a loss of data. Data storage in 
a memory type flip-flop as presented in [2) and [3] is more 
reliable. Fig. 3 depicts the circuit schematic. The memory 
type flip-flop comprises two ED-DCFL inverters. These DCFL 
inverters never will reach 30 GHz operation, but in this case 
the outputs are directly driven. Thus the gate widths of the flip-
flop transistors should be small in comparison to the. driving 
buffers. To switch the flip-flop symmetrically two ring oscilla-
tors were used, each consisting of one SBFL inverter and two 
source followers. The push-pull stages of the SBFL inverters 
guarantee low output inpedance and a high voltage swing. 
Because of finite rise and fall times, an appropriate delay 
in the inverter output signals is very important for stable 
operation of the divider. Therefore a second source follower 
was used in the ring oscillator chain. 
The gate widths of the transfer transistors are a trade-off 
between a high on-conductance and a low capacitive load for 
the driving source follower. 
The circuit design was optimized by SPICE simulation on 
the basis of an in-house developed HEMT network model 
presented earlier [ 14]. All transistors have gate lengths of 
0.2 p,m; the optimized values for the gate width are shown 
in the figure. 
For higher frequencies 1/3 and 1/4 division can be expected, 
but the appropriate bandwidth for stable operation declines. 
IV. RESULTS 
Fig. 4 is a micrograph of the divider circuit. The chip size 
excluding buffers is approximately 150 J.IUl x 200 11m. The 
THIEDE tt til.: DYNAMIC REQUENCY DIVIDER 
Fig. 4. Micrograph of the divider circuit. 
7E5mv 
Main Size 
20ps/ dlv 
Fij! . 5. Measured pulse diagram of a 34-GHz input and lhe 17-GHz output 
of the dynamic frequency divider. 
input is applied to the bond pads using a coplanar line and 
on chip tenninated to match 50 n. 
Measurements carried out on the digital dynamic frequency 
divider show a lower limit for stable operation of 18 GHz. 
A value of 34 GHz for the maximum input frequency was 
obtained. Fig. S shows the pulse diagram of the 34-GHz input 
;md 1he 17-GHz output. As far as we know this is the best result 
cv<:r reponed for HEMT circuits. and similar to the frequency 
limit shown by use of AIGaAs/GaAs HBT's. 
Between 36 GHz and the 40-GHz limit of the test equip-
ment, an operation modulus of 1/3 division could be shown. 
The divider can operate with single-phase input. The input 
~oltage swing is about I V at 18 GHz and decreases as the 
frequency increases. 
1169 
Both single-phase and differential outputs are possible. The 
circuit runs at a power supply of VDD = 2 V and Vss = -2 Y. 
A power consumption as low as about 250 mW was obtained 
for the divider without buffers. 
A fully functional yield greater than SO% was obtained. 
V. SuMMARY 
The design and perfonnance of a dynamic frequency divider 
was presented. This digital IC demonstrates the abiliry of our 
AIGaAs/GaAs/AIGaAs quantum-well FET's with gate lengths 
of 0.2 f.Lm. Stable operation was achieved in the frequency 
range from 18 GHz up to 34 GHz with a power consumption 
of 250 mW. As far as we know, this is the best result ever 
reponed for HEMT circuits, and it is similar to the frequency 
limit achieved by use of AIGaAs/GaAs HBT's. 
A CKNOWLEDGMENT 
The authors are grateful to the entire staff of the laboratory. 
They especially want to thank H. S. Rupprecht for his directing 
and continuous encouragement and T. Jakobus for his expen 
technology management. 
R EFERENCES 
Ill J. F. Jensen et al.. "26 GHz GaAs room-temperature dynamic divider 
c ircuit," in IEEE GaAs IC Symp. Dig .• 1987. pp. 20 1-203. 
)2} T. Saito tt al .. "0.251'm gate inverted HEMTs for an ultra-high speed 
DCFL dynamic frequency divider." in IEEE GaAs IC Symp. Dig .. 1989. 
pp. 117-120. 
[3) T. lchioka et a/., "An uhra·high speed DCFL dynamic frequency 
divider." IEEE Microwa•·e and Millimeter-Wow• Monolithic Circuits 
Symp. Dig .. 1989. pp. 61-64. 
[4] A. Felder et a/ .• ''5 to 40 Gb/s Si ICs in selective epitaxial bipolar 
technology," in Tech. Dig. IEEE 1111. Solid-State Circuits Conf. 1993. 
pp. 156-157. 
[5] Y. Yamauchi et a/ .. "A 34.8 GHz 1/4 static frequency divider using 
AIGaAs/GaAs HBTs." in IEEE GaAs IC Symp. Dix .. 1989. pp. 12 1- 124. 
[6} J. F. Jensen et al .. "39.5 GHz static frequency divider implemented in 
AllnAs/ 
GalnAs HBT technology," in IEEE GaAs /C Symp. Dig .. 1992. pp. 
101-104. 
[71 K. Koehler n a/ .. ''Advanced high e lectron concentration GaAs/ 
AI, Ga1- ..-As pulse-doped douhle heterostructure for device applica-
tion:· in Proc. lnt. Symp. 011 Gallium Arse11ide a11d Related Compounds. 
1990. lnst. Phys. Conf. Ser.. vol. 112. 1990, pp. 521-526. 1990. 
(8} A. Huel smann er al .. "E-beam direct-write in a dry-etched recess gate 
HEMT process for GaAs/AIGaAs circuits." Japan. J. Appl. Phys .. vol. 
29, no. 10, pp. 2317-2320, 1990. 
(91 M. Berroth er al .. "A 2.5 ns S x S·b parallel multiplier using O.Sjcnl 
GaAS/GaAIAs heterostructure field effect transistors," Microelectron. 
Eng .. vol. 15. pp. 327-330. 1991. 
[101 U. Nowotny et al .. "20 Gbil/s 2 : 1 mul!iplexcr using 0.3/tm gate 
length double pulse doped quantum well GaAs/AIGaAs transistors," 
Microelecrron. £11g .. vol. 15. pp. 323- 326. 1991. 
[II I W. Bischof et of.. "Modelling and realization of a monolithic 27 GHz 
HEMT an1plifier in coplanar waveguide technology," in Prnc. European 
Microwa>·e Conf.. 1990, pp. 943-948. 
( 12) V. Hurm et al .. "10 Gbil/s monolithic integrated optoelec1ronic receiver 
using an MSM photodiode and AlGaAs/GaAs HEMTs." Microele<·trotl. 
Eng .. vol. 15, pp. 275-278. 1991. 
(131 A. l11iede er at .. "16 x 16 bit parallel multiplier based on 6 k gate array 
with 0.3/tm AIGaAs/GaAs quantum well lransistors.'' Electron. Lm .. 
vol. 28, no. II . pp. 1005-1006. 1992. 
[14} M. Berroth and R. Bosch, "High-frequency equivalent circuit of GaAs 
FETs for large-signal applications.'' IE££ Miao..-a•·e TheOt:r Tech .. vol. 
39. no. 2. pp. 224-229. 1991. 


An 18-34-GHz dynamic frequency divider based on 0.2-&#956;m AlGaAs/GaAs/AlGaAs quantum-well transistors

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An 18-34-GHz dynamic frequency divider based on 0.2-μm AlGaAs/GaAs/AlGaAs quantum-well transistors

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An 18-34-GHz dynamic frequency divider based on 0.2-&#956;m AlGaAs/GaAs/AlGaAs quantum-well transistors

Abstract

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Full text

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An 18-34-GHz dynamic frequency divider based on 0.2-μm AlGaAs/GaAs/AlGaAs quantum-well transistors