Thin Film Transistors have been fabricated in 0.2 urn thick polycrystalline silicon. NMOS and PMOS devices were fabricated on four groups of substrates. One group was processed with as deposited polysilicon and three of the substrates received high dose implants of Si and/or Ge prior to anneal. The Si implants were designed to amorphize the film by a process known as Seed Selection through Ion Channeling (SSIC), and the Ge was implanted just below the surface to enhance transistor characteristics. Two of the groups, one which received Ge implanted just below the surface and the other no implant at all, did not show much of any improvements in either the NMOS or the PMOS devices. Wafers that received double Si implants prior to substrate anneal, allowed the NMOS devices to exhibit better transistor qualities than any of the other implants, while the PMOS devices exhibited very poor qualities. Substrates that received a high energy high dose Si implant and Ge implanted just below the surface at a high dose to create a Si-Ge channel, demonstrated a 100% increase in hole mobility on 2 urn channel length devices over the double Si implanted substrates. The drain current of the Si-Ge PMOS devices was -260 uA as compared to -16 uA for the double Si implanted substrates for VGS=-7 V at VDS=3.0 V. The subthreshold swing was much larger at 2.1 V/dec for the Si- Ge channel PMOS devices as compared to and average of about 0.5 V/dec for all the other PMOS devices. The undesirable leakage observed in the subthreshold swing can be attributed to the grain structure of the Si-Ge layer in the channel. These effects can be minimized by further enhancement of grain sizes and passivation of the grain boundaries
