One of the most important considerations for the current VLSI/SOC design is power, which can be classified into power analysis and optimization. In this survey, the main concepts of power optimization including the sources and policies are introduced. Among the various approaches, dynamic power management (DPM), which implies to change devices states when they are not working at the highest speed or at their full capacity, is the most efficient one. Our explanations accompanying the figures specify the abstract concepts of DPM. This paper briefly surveys both heuristic and stochastic policies and discusses their advantages and disadvantages

Liu, Bin

Wang, Xiaojun

Weng, Li-Chuan

English

Name not available

A Survey of Dynamic Power Optimization TechniquesLi-Chuan Weng††School of Electronic EngineeringDublin City UniversityDublin, Irelandwengli@eeng.dcu.ieXiaoJun Wang† Bin Liu§§Department of Computer ScienceTsingHua UniversityP.R. ChinaAbstractOne of the most important considerations for thecurrent VLSI/SOC design is power, which can be clas-siﬁed into power analysis and optimization. In this sur-vey, the main concepts of power optimization includingthe sources and policies are introduced.Among the various approaches, dynamic powermanagement (DPM), which implies to change devicesstates when they are not working at the highest speedor at their full capacity, is the most eﬃcient one. Ourexplanations accompanying the ﬁgures specify the ab-stract concepts of DPM. This paper brieﬂy surveys bothheuristic and stochastic policies and discusses their ad-vantages and disadvantages.1. IntroductionThe average power consumption of CMOS can bemodelled with the following equation [5, 23, 24, 4, 28].Pavg = PDynamic + PStatic (1)The dominate part of Pavg is the dynamic power,PDynamic, caused by Pswitching and Pshort−circuit.Here we emphasize on the minimization of Pswitchingwhich can be expressed by the following equation:Pswitching = K · Cout · Vdd · Vswing · f (2)In most of the cases, Vswing = Vdd, therefore the equa-tion 2 can be re-written asPswithcing ≈ K · Cout · V 2dd · f (3)From the equation 3, there are four parameters thatwe can consider to change [15]. i.e. the node transitionactivity factor K, load capacitance Cout, supply voltageVdd, and working frequency f .2. Strategies2.1. by SourcesAs indicated in equation 3, the switching power con-sumption decreases quadratically with the decrease ofVdd and decreases linearly with the decrease of theother parameters. Therefore, there are various ap-proaches depending on diﬀerent parameters.Swing voltage Vswing: Because most of the timeVswing equals to Vdd, most researches concentrate onlowering supply voltage, although there are some re-searches try to decrease the swing voltage from therange of Vgnd to VddH to the range of Vgnd to VddL[22].Supply voltage Vdd: The policies applied on thisparameter including supply shutdown, variable voltage,and partial shutdown. Because of the diﬀerent fea-tures of computations that can be either event-driven1in-nature or continuous 2 in nature, we use diﬀerentapproaches.For example, we decrease the power consumptionof an event-driven system by system shutdown whenit is at inactivity periods, and reduce the power con-sumption of a continuous system by scaling the supplyvoltage according to the characteristic of unbalancingworkload. The concerns of the shut down strategies are”how” and ”when” to apply. While the ﬁrst issue canbe done by either stop the clock or switch oﬀ the sup-ply voltage, the second one has to concern more compli-cated problems. On the other hand, though the scalingof supply voltage helps continuous system to minimizethe power consumption, there are some overheads dueto the increase of Td, the CMOS circuit delay. In orderto solve this problem, some researches use higher sup-1Event-driven means the computation activities are triggeredby external events [5]2Continuous means the continuous computation e.g. the ap-plications in speech coding [5].Proceedings of The 3rd IEEE International Workshop on System-on-Chip  for Real-Time Applications ISBN 0-7695-1929-6/03 $17.00 © 2003 IEEEAuthorized licensed use limited to: DUBLIN CITY UNIVERSITY. Downloaded on July 20,2010 at 12:41:35 UTC from IEEE Xplore.  Restrictions apply. ply voltage in the critical path and use lower voltage inothers so that the system can ﬁnish the works withingiven time while save the power consumed during theprocess [31, 6, 7, 14, 32, 10, 11].Eﬀective capacitance Ceff=K · Cout: There aresome approaches try to lower the eﬀective capacitanceCeff by lowering the transitions parameter K, or min-imizing the load capacitor Cout. Lowering the switch-ing activities of the capacitors in a system can beachieved by restructuring the computation, communi-cation, memory storage and hierarchy, and changingthe data encoding, etc. [30].Clock frequency f : The observation that reduc-ing the clock frequency can decrease power dissipationis very intuitive, but it also implies the working time isextended i.e. the performance is inﬂuenced. The tech-niques such as clock gating, variable frequency, andclock generator shutdown all belong to this approach.Further discussion can be found in [5, 20].2.2. Power managementIn general, there are two groups of power minimiza-tion techniques, static and dynamic [17]. The formeris applied during the design time and the latter man-ages to save the power consumption by scheduling theruntime behavior. As the policy dynamically changesthe system’s states, we call them Dynamic power man-agement approaches, (DPM).The basic assumption of DPM is, though the sys-tems are designed to be able to work at peak state,most of the time they are not working at their full ca-pacity [3]. As a result, DPM could save the power con-sumption by selectively placing components into lowpower consumption states such as idle or sleep [30, 29].Prediction accuracy and power savings are the two cri-teria used to assess if the policy is appropriate or not.The heart of DPM is power manager (PM) which doesnot have a ﬁxed shape. PM is an abstract idea existsin the system; it can be implemented in either softwareor hardware. In software, it can be applied on Oper-ating System (OS) or written in hardware descriptionlanguage; in hardware, it can be applied to a circuitmodule or a chip [3].3. DPM techniquesThe basic idea of DPM is that, since the workloadof a system is usually not constant, therefore, if we canpredict its status then we can reduce the power dissipa-tion by some means[1]. Though leave the device ”ON”when there is no workload wastes power, simply shut-ting oﬀ components as soon as they are not used mightbe counter productive as illustrated in ﬁgure 1. Thisoccurs when the system needs the idled componentsagain within very short time. It is due to the fact thatit takes time to recover their states and sometimes thepower saved is less than the power consumed duringstates transitions[3, 17].The concept of break-even time, i.e. the minimumlength of idle time to achieve power saving [17], playsan important role here. If we do not consider the draw-back of wake-up delay but only see from the energypoint of view, the system should shutdown only whenidle period t is longer than Tbe. Equation 4 explainsthe origin of Tbe.Pw · t ≥ Esd + Ewu + Ps · (t− Tsd − Twu)t ≥ Esd + Ewu − Ps · (Tsd + Twu)Pw − PsTbe =Esd + Ewu − Ps · (Tsd + Twu)Pw − Ps(4)In short, because of the latency penalty for wake-up,PwidlesleepingEsdactivePsTwuTsd Tbepowerworkingworking working EwuPw: working powerPs : sleeping powerTsd : shutdown delayTwu: wake up delayTbe : break even timeEsd : shutdown energy consumptionEwu : wake up energy consumptiontimeFigure 1. Break-even timesystem should only be shutdown when t ≥ Tbe. Forsame idle time, longer break-even time Tbe means lesspower saving due to the overhead for recovering state[1].3.1. Heuristic policies”When to shutdown” is the concern of heuristic poli-cies [5], which can be classiﬁed into time-out and pre-dictive approaches.3.1.1. Timeout techniquesThe time-out policies can be either adaptive or non-adaptive[27, 26]. In general, both policies change thesystem into idle state after the system is not perform-ing any task for a period of time Tpre. In non-adaptivetechnique, Tpre is ﬁxed, so it is also called ﬁxed time-out policy. It is the simplest DPM policy [18] that usesProceedings of The 3rd IEEE International Workshop on System-on-Chip  for Real-Time Applications ISBN 0-7695-1929-6/03 $17.00 © 2003 IEEEAuthorized licensed use limited to: DUBLIN CITY UNIVERSITY. Downloaded on July 20,2010 at 12:41:35 UTC from IEEE Xplore.  Restrictions apply. a time out value and assumes the system will continueto be idle for at least the break-even time after idlefor the time out period [17], see ﬁgure 2. In the adap-tive approach, Tpre can be adjusted by using the recentcomputation history to predict if the idle time will belonger than the break-even time or not.Both adaptive and non-adaptive time-out techniqueshave two main disadvantages, one is the predictionmust be accurate or it will lose rather than save power,and the other one is that there is still some power con-tinuously dissipated during the waiting period [13, 1].This method works when the idle time is long in aver-age but does not perform very well on the other wayround [13].TtoactiveidletimePwsleepingTwuTsdTto : fixed timeoutpowerPs workingworkingEwuEsdFigure 2. Fixed time-out3.1.2. Predictive techniquesIn stead of waiting for a ﬁxed time period as time-outpolicies, the predictive techniques force the power statechanges into low-power state as soon as it is predictedto stay idle for longer than break-even time, Tbe [30].Some policies try to avoid the waiting time of wakingup as in ﬁxed time-out policies by using prediction ofthe workloads [13], see ﬁgure 3.However, from ﬁgure 4 we can see wrong predic-tions still waste power which might happen either whenthe component is forced to transit into idle too late orwake up too early [17]. Therefore, in order to avoidthe overhead due to the wrong prediction, it becomesnecessary to improve the hit ratio and reduce the delayoverhead [13].3.2. Stochastic techniquesIn order to guarantee optimal result, there are somepolicies using stochastic process to model the the sys-tem and workload, i.e. the arrival of requests andTpredpre-wakeupforce to enter sleep modeactivetimesleepingsave the time of waitingTpred : predicted idle periodidlepowerPsPwTwuTsdworkingworking EsdEwuFigure 3. Predictive policy – correct predic-tionwaste powerreal idle periodTpredactivetimesleepingpowerPsPwTwuTsdpre-wakeupforce to enter sleep modeworkingworkingwaste powerEwuEsdFigure 4. Predictive policy – wrong predictiondevice power-state changes [17, 29]. The current ap-proaches are mostly based on Markov processes, includ-ing stationary and non-stationary Markov models, dis-crete time and continuous-time Markov models, semi-Markov models and time-indexed semi-Markov models.Comparing to the stationary stochastic policy, thenon-stationary stochastic policy generally has bet-ter power saving abilities when deal with the non-stationary wokloads due to its adaptive schemes [17].The Discrete time Markov models evaluate the systemat periodic time points, so it is not suitable for event-driven cases. Continuous time Markov models do nothave the periodic limitation of the discrete time mod-els but they require all the stochastic processes to beexponential. In order to relax the exponential distribu-tions requirements, semi-Markov models are proposed,in which one of the stochastic process needs not to be ofexponential distribution. Time-indexed semi-Markovmodels can have multiple non-exponential processesbut it becomes even more complex.Proceedings of The 3rd IEEE International Workshop on System-on-Chip  for Real-Time Applications ISBN 0-7695-1929-6/03 $17.00 © 2003 IEEEAuthorized licensed use limited to: DUBLIN CITY UNIVERSITY. Downloaded on July 20,2010 at 12:41:35 UTC from IEEE Xplore.  Restrictions apply. 4. Discussion and conclusionWhile many studies focused on the high performancerequirement, low-power system design now gets moreand more attention because of the growing demandsfrom portable computing and communication devices[30]. Detailed discussion of power optimization can befound in [9, 23, 2, 1, 17, 19, 3, 18].The short discussion of resources of average powerdissipation oﬀers the overview of the concerns of powermanagement. For systems with diﬀerent characteris-tics we could apply either shutdown or scheduling tech-niques which are based on the consideration of supplyvoltage Vdd and clock frequency f . To eﬃciently ap-ply shutdown, scheduling, and state transition, it isnot trivial but complicated. The existing approachesare numerous and can be generally classiﬁed by thenatures of the methods as heuristic and stochastic ap-proaches. There is no known ideal solution yet, manyof the methods are data or system dependent and someare too complex though their dependency are superiorthan the others.This survey only discusses the optimization aspectbut not the other important element, power analysis.[21, 25, 12, 8, 16] cover the induction of this aspect.The demand of power management is increasing andmore support in both analysis and optimization arenecessary.References[1] L. Benini, A. Bogliolo, and G. D. Micheli. A surveyof design techniques for system-level dynamic powermanagement. Very Large Scale Integration (VLSI)Systems, IEEE Transactions on, 8(3):299–316, June2000.[2] L. Benini and G. de Micheli. System-level power opti-mization: techniques and tools. ACM Transactions onDesign Automation of Electronic Systems (TODAES),5(2):115–192, 2000.[3] L. Benini, R. Hodgson, and P. Siegel. System-levelpower estimation and optimization. In Proceedings1998 international symposium on Low power electron-ics and design, pages 173–178. ACM Press, 1998.[4] L. Benini and G. D. Micheli. Dynamic power man-agement – design techniques and CAD tools. KluwerAcademic Publishers, 1998.[5] A. P. Chandrakasan and R. W. Brodersen. Low powerdigital CMOS design. Kluwer Academic Publishers,1995.[6] J. Chang and M. Pedram. Energy minimization usingmultiple supply voltages. In Proceedings of the 1996international symposium on Low power electronics anddesign, pages 157–162. IEEE Press, 1996.[7] J.-M. Chang and M. Pedram. Energy minimizationusing multiple supply voltages. Very Large ScaleIntegration (VLSI) Systems, IEEE Transactions on,5(4):436–443, 12 1997.[8] R. Y. Chen, M. J. Irwin, and R. S. Bajwa.Architecture-level power estimation and design exper-iments. ACM Transactions on Design Automation ofElectronic Systems (TODAES), 6(1):50–66, 2001.[9] S. Devadas and S. Malik. A survey of optimizationtechniques targeting low power vlsi circuits. In Pro-ceedings of the 32nd ACM/IEEE conference on Designautomation conference, pages 242–247. ACM Press,1995.[10] S. Dhar and D. Maksimovic. Low-power digital ﬁlter-ing using multiple voltage distribution and adaptivevoltage scaling (poster session). In Proceedings of the2000 international symposium on Low power electron-ics and design, pages 207–209. ACM Press, 2000.[11] M. Donno, L. Macchiarulo, A. Macii, E. Macii, andM. Poncino. Enhanced clustered voltage scaling forlow power. In Proceedings of the 12 th ACM Sym-posium on Great Lakes Symposium on VLSI, pages18–23. ACM Press, 2002.[12] S. Gupta and F. N. Najm. Power macromodeling forhigh level power estimation. In Proceedings of the 34thannual conference on Design automation conference,pages 365–370. ACM Press, 1997.[13] C.-H. Hwang and A. C.-H. Wu. A predictive systemshutdown method for energy saving of event-drivencomputation. In Proceedings of the 1997 IEEE/ACMinternational conference on Computer-aided design,pages 28–32. IEEE Computer Society, 1997.[14] M. C. Johnson and K. Roy. Datapath scheduling withmultiple supply voltages and level converters. ACMTransactions on Design Automation of Electronic Sys-tems (TODAES), 2(3):227–248, 1997.[15] J. B. Kuo and J.-H. Lou. Low-voltage CMOS VLSIcircuits. Wiley-Interscience, 1999.[16] M. Lajolo, A. Raghunathan, S. Dey, and L. Lavagno.Cosimulation-based power estimation for system-on-chip design. Very Large Scale Integration (VLSI) Sys-tems, IEEE Transactions on, 10(3):253–266, 6 2002.[17] Y.-H. Lu and G. D. Micheli. Comparing system-levelpower management. IEEE Design and Test of Com-puters, 18(2):10–19, March-April 2001.[18] E. Macii. Dynamic power management of elec-tronic systems. IEEE Design and Test of Computers,18(2):6–9, March-April 2001.[19] E. Macii, M. Pedram, and F. Somenzi. High-level power modeling, estimation and optimization.Computer-Aided Design of Integrated Circuits andSystems, IEEE Transactions on, 17(11):1061–1079,November 1998.[20] T. Martin and D. Siewiorek. A power metric for mo-bile systems. In Proceedings of the 1996 internationalsymposium on Low power electronics and design, pages37–42. IEEE Press, 1996.Proceedings of The 3rd IEEE International Workshop on System-on-Chip  for Real-Time Applications ISBN 0-7695-1929-6/03 $17.00 © 2003 IEEEAuthorized licensed use limited to: DUBLIN CITY UNIVERSITY. Downloaded on July 20,2010 at 12:41:35 UTC from IEEE Xplore.  Restrictions apply. [21] F. N. Najm. Towards a high-level power estimationcapability. In Proceedings 1995 international sympo-sium on Low power design, pages 87–92. ACM Press,1995.[22] J. Pangjun and S. S. Sapatnekar. Low-power clock dis-tribution using multiple voltages and reduced swings.Very Large Scale Integration (VLSI) Systems, IEEETransactions on, 10(3):309–318, 6 2002.[23] M. Pedram. Power minimization in ic design: princi-ples and applications. ACM Transactions on DesignAutomation of Electronic Systems (TODAES), 1(1):3–56, January 1996.[24] J. M. Rabaey and M. Pedram. Low power designmethodologies. Kluwer Academic Publishers, 1996.[25] A. Raghunathan, S. Dey, and N. K. Jha. Register-transfer level estimation techniques for switching ac-tivity and power consumption. In Proceedings ofthe 1996 IEEE/ACM international conference onComputer-aided design, pages 158–165. IEEE Com-puter Society Press, 1996.[26] D. Ramanathan. High-level timing and power anal-ysis of embedded systems. PhD thesis, University ofCalifornia, Irvine, 2000.[27] D. Ramanathan and R. Gupta. System level onlinepower management algorithms. In Proceedings of theconference on Design, automation and test in Europe,pages 606–611. ACM Press, 2000.[28] K. Roy and S. C. Prasad. Low-power CMOS VLSIcircuit design. John Wiley & Sons, Inc., 2000.[29] T. Simunic. Energy eﬃcient system design and uti-lization. PhD thesis, Stanford University, February2001.[30] M. B. Srivastava, A. P. Chandrakasan, and R. W.Brodersen. Predictive system shutdown and otherarchitectural techniques for energy eﬃcient pro-grammable computation. Very Large Scale Integration(VLSI) Systems, IEEE Transactions on, 4(1):42–55,March 1996.[31] K. Usami and M. Horowitz. Clustered voltage scalingtechnique for low-power design. In Proceedings 1995international symposium on Low power design, pages3–8. ACM Press, 1995.[32] K. Usami, K. Nogami, M. Igarashi, F. Minami,Y. Kawasaki, T. Ishikawa, M. Kanazawa, T. Aoki,M. Takano, C. Mizuno, M. Ichida, S. Sonoda, M. Taka-hashi, and N. Hatanaka. Automated low-power tech-nique exploiting multiple supply voltages applied to amedia processor. In Custom Integrated Circuits Con-ference, pages 131–134. IEEE, 1997.Proceedings of The 3rd IEEE International Workshop on System-on-Chip  for Real-Time Applications ISBN 0-7695-1929-6/03 $17.00 © 2003 IEEEAuthorized licensed use limited to: DUBLIN CITY UNIVERSITY. Downloaded on July 20,2010 at 12:41:35 UTC from IEEE Xplore.  Restrictions apply. 

A survey of dynamic power optimization techniques

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DCU Online Research Access Service

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Datapath scheduling with multiple supply voltages and level converters.

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Low-power digital ﬁltering using multiple voltage distribution and adaptive voltage scaling (poster session).

Power macromodeling for high level power estimation.

Power minimization in ic design: principles and applications.

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Registertransfer level estimation techniques for switching activity and power consumption.

System level online power management algorithms.

System-level power estimation and optimization.

System-level power optimization: techniques and tools.

A survey of dynamic power optimization techniques

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