In this paper, we present a 10/30GHz MMIC Tripler, an X-band VCO and a frequency divider using a 0.35 µm, 60 GHz-fMAX MMIC BiCMOS SiGe technology. The Tripler exhibits a conversion gain of -5 dB and a low additive phase noise of –143dBc/Hz at a frequency offset of 100kHz is anticipated. In order to drive this Tripler, the design of a MMIC X-band VCO and its measured performance (0.8GHz tuning range, -5 dBm output power and –87dBc/Hz phase noise @ 100kHz of carrier) is also reported. This X band VCO can also drive a frequency divider, developed in the same technology. The assembling of these circuits allows the design of a 2 GHz frequency synthesizer. Measurements have shown a phase noise of -99dBc/ Hz at a frequency offset of 100kHz. Therefore, this paper demonstrates the great capabilities of BiCMOS SiGe MMIC technology about frequency synthesis ranging from 2GHz to 30GHz

Coustou, A.

Dubuc, D.

Graffeuil, J.

Llopis, O.

Plana, R.

Sie, M.

Tournier, E.

English

AMS Acta

Electrothermal and trapping effects characterisation of
AlGaN/GaN HEMTs
C. Charbonniaud, S. De Meyer, R. Quéré, JP. Teyssier
IRCOM, CNRS UMR 6615, University of Limoges, 19100 Brive, France
Abstract — This paper presents a systematic analysis of
the two kinds of traps encountered in AlGaN/GaN HEMTs.
It is shown that passivation is very efficient to minimize the
surface trap effects but has little effect on the buffer traps.
Those ones can only be eliminated through the development
of high purity substrates. Moreover thermal I-V and
microwave behaviour of such transmissions is investigated
through the use of a pulse-measurement system.
I. INTRODUCTION
Wide band-gap transistor technologies such as
AlGaN/GaN HEMTs are very promising for radio
frequency and microwave power generation [1]. Indeed
they present high breakdown voltages as well as high
current densities. Moreover they can also work at high
temperatures. However, parasitic effects induced by
trapping phenomena severely limit the power
performances of these transistors [2], [3].
Pulsed I.V. measurements have demonstrated their
usefulness for characterising such trapping behaviour [4].
In this paper we show that two kinds of measurements
allow to discriminate the two kinds of traps that can be
encountered in AlGaN/GaN devices: surface traps and
buffer or substrate traps. Effects corresponding to the
former type can be minimised by passivation techniques
while the latter are much more difficult to eliminate.
Measurements of 2x50 µm AlGaN/GaN transistors grown
on various substrates have been carried out and compared.
Moreover thermal behaviour of such transistors is of
prime importance due to the high power densities that can
be reached. Temperature dependent pulsed measurements
allow to derive electro-thermal characteristics of these
transistors.
II. TRAPPING EFFECTS CHARACTERISATION
The trapping effects correspond to the existence of
energy states which can be occupied by holes or electrons
in the gap. These holes or electrons are then maintained in
these levels during an important lapse of time and cannot
take part in the conduction, hence the term ‘trap’. They
generally result in the presence of impurities or defects in
the crystalline network of the material they are composed
of. These phenomena alter the electric behaviour of the
transistor at microwave frequencies.
In order to determine the trapping effects thanks to the
pulse measurement, we must establish a rigorous
measuring protocol so as to differentiate the surface
trapping effects (gate-lag) and the buffer trappings (self-
backgating) as accurately as possible. First of all it is
necessary to make sure that the duration of the pulses is
lower than the emission time constant of the traps. Thus
we chose a pulse duration equivalent to 400 ns with a
recurrence equal to 6µs. Finally, to make sure that the
differences recorded in the measures are those coming
from trapping effects, we must work with a constant
temperature, hence with a constant dissipated power.
The two kinds of ionised traps are figured at Fig. 1.
Surface traps results from deep level acceptors that are
ionised when the gate voltage is set below pinch-off [5].
Buffer or substrate traps are localised near the channel and
are ionised when an electric field is set up in the channel
direction resulting from a Vds voltage different from zero.
Source Gate
Canal GaN
buffer
Drain
AlGaN
Fig. 1. Localisation of trap effects
A. Characterisation Of Gate-Lag Phenomenon
The ‘gate-lag’ phenomenon is mainly attributed to
surface trapping effects. To determine these surface
trapping effects, we make two series of pulse
measurements with an identical dissipated power
(Pdiss = 0W). For that, we choose two quiescent biases
equivalent to (Fig. 2) :
Vgs0 = Vp, Vds0 = 0V (1)
Vgs0 = 0V, Vds0 = 0V (2)
Therefore we can say that in both cases we work with an
identical power equivalent to zero; consequently a
difference between both I(V) characteristics implies the
presence of gate-lags.
In this case as the quiescent Drain voltage is equal to
zero, we can make the assumption that the number of
ionised buffer traps is low.
11th GAAS Symposium - Munich 2003 201
Vds
t
t
Vgs0=Vp
Vgsi
Vdsi
Vds0=0V
Vgs0=0V
Vgs
Fig. 2. Method of measurement to determine the gate-lag
effects
We apply the measurement method described at Fig.2
to two AlGaN/GaN 2x50 µm transistors on SiC substrate.
The difference between these two transistors is that one of
them is passivated and the other one is not (Fig. 3). To
realise the measures, we bias the passivated transistor,
using two different quiescent biases :
Vgs0 = -7V, Vds0 = 0V
Vgs0 = 0V, Vds0 = 0V
with a –7V ≤ Vgsi ≤ 2V by step of 1V.
Then we bias the second transistor (which has not been
passivated) with, again, two different quiescent biases :
Vgs0 = -3V, Vds0 = 0V
Vgs0 = 0V, Vds0 = 0V
with a -3V ≤ Vgsi ≤ 1.5V by step of 0.5V.
Consequently we work with Pdiss = 0W.
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
-10 0 10 20 30 40 50 60
Id
en
A
m
pe
re
s
Vds en Volts
Vgs0 = -3 V, Vds0 = 0 V
Vgs0 = 0 V, Vds0 = 0 V
SiC substrate without passivation
-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
-10 0 10 20 30 40 50 60
Id
en
A
m
pe
re
s
Vds en Volts
Vgs0 = -7 V, Vds0 = 0 V
Vgs0 = 0 V, Vds0 = 0 V
SiC substrate with passivation
a)
b)
Fig. 3. Output I(V) characteristic for AlGaN/GaN 2x50
HEMTs grown on SiC substrate a) with passivation
b) without passivation
We can notice that there is a strong decrease of drain
current on the non-passivated transistor, whereas on the
passivated transistor the output current decreases slightly.
However, even in this case of the strong decrease of the
drain current, the knee-voltage of the HEMT is not
modified by the quiescent gate bias.
As a consequence, the passivation is a good mean to
limit the gate-lag effects.
B. Characterisation Of Self-Backgating Phenomenon
Just like the gate-lag phenomenon, the self-backgating
phenomenon manifests itself through slow transient
effects of the drain current , and therefore it creates a
limitation of the output current especially for Vds voltages
that are below the quiescent Drain voltage Vds0. This
effect is due to traps in the buffer. The self-backgating
effects appears when the electrical field between the drain
and the source increases suddenly.
Indeed, the electrons from the channel are injected in the
buffer and are quickly trapped charging the buffer
negatively. Thus this space charge region acts as a back-
gate. Consequently in order to maintain the global
neutrality, the electron sheet density in the channel
decreases leading to a decrease of the drain current.
Just like before, in order to determine the self-
backgating effects, we will make two series of pulse
measurements with an identical dissipated power equal to
zero. To achieve this, we choose two quiescent biases
equal to (Fig. 4) :
Vgs0 = Vp, Vds0 = 0V (3)
Vgs0 = Vp, Vds0 >> 0V (4)
Vds
Vds0
Vdsi
Vds0=0V t
Vgs
Vgs0=0V
Vgsi
Vgs0=Vp
t
Fig. 4. Method of measurement to determine the self-
backgating effects
We apply the measurement method described before to
the same passivated transistor that was shown in Fig.3-a.
To realize the measures, we bias this transistor, using two
different quiescent biases :
Vgs0 = -7V, Vds0 = 0V
Vgs0 = 7V, Vds0 = 25V
with a –7V ≤ Vgsi ≤ 2V by step of 1V.
The quiescent gate bias was set to –7V and the
characteristic shown in Fig. 5 exhibits a large increase of
the knee voltage. This shows that despite a good
passivation, there remains a reduction in the output power
due to the presence of buffer traps.
Indeed applying a large electric field between drain and
source leads to the ionization of a large number of traps
that are located near the channel. It can be observed that
above the quiescent drain bias, the characteristics are
almost identical. This fact reveals that the number of
11th GAAS Symposium - Munich 2003202
ionized traps depends on the maximum value of the bias
voltage Vdsi rather than the average value Vds0 [4].
-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
-10 0 10 20 30 40 50
Id
en
A
m
pe
re
s
Vds en Volts
25
Vgs0 = -7 V, Vds0 = 0 V
Vgs0 = -7 V, Vds0 = 25 V
∆ I
∆ V
Fig. 5. Output I(V) characteristic for AlGaN/GaN 2x50
HEMTs grown on SiC substrate
This is due to the difference between the capture time
constant and the emission time constant of the traps.
The same experiments have been performed on other
transistors grown on sapphire and Si substrates. The
transistor grown on sapphire was biased using two
different quiescent biases (Fig. 6) :
Vgs0 = -5V, Vds0 = 0V
Vgs0 = 5V, Vds0 = 20V
with a –5V ≤ Vgsi ≤ 1V by step of 1V,
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
-5 0 5 10 15 20 25 30 35 40
Id
en
A
m
pe
re
s
Vds en Volts
20
Vgs0 = -5 V, Vds0 = 0 V
Vgs0 = -5 V, Vds0 = 20 V
∆ I
∆ V
Fig. 6. Output I(V) characteristic for AlGaN/GaN 2x50
HEMTs grown on Sapphire substrate
and the transistor grown on Si was biased in the same way
with (Fig. 7) :
Vgs0 = -6V, Vds0 = 0V
Vgs0 = 6V, Vds0 = 20V
with a –6V ≤ Vgsi ≤ 2V by step of 1V.
-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
-5 0 5 10 15 20 25 30 35 40 45 50
Id
en
A
m
pe
re
s
Vds en Volts
20
Vgs0 = -6 V, Vds0 = 0 V
Vgs0 = -6 V, Vds0 = 20 V
∆ I
∆ V
Fig. 7. Output I(V) characteristic for AlGaN/GaN 2x50
HEMTs grown on Si substrate
We can remark that whatever the nature of the substrate,
the buffer trapping effects (self-backgating) are very
present. As a matter of fact, we can see that the drain
current is really affected by this bias change at dissipated
power equal to zero.
The effects of traps can be evaluated by measuring the
decrease of the maximum available drain current (∆I) and
the increase of the knee-drain voltage (∆V). Those
quantities are evaluated along an ideal load-line that
provides the maximum of output power in a deep AB
class / B class. Table I summarizes the results obtained.
AlGaN/GaN HEMT 2X50
SiC
substrate
Sapphire
substrate
Si
substrate
∆I (mA) 18.33 21.35 10.83
∆V (V) 3.24 3.64 1.48
TABLE I
MEASURES OF VOLTAGE/CURRENT DIFFERENCES
DUE TO DRAIN TRAPS ON DIFFERENT SUBSTRATES
As can be noticed from the previous figures, this
modification of the output characteristics strongly affects
the available output power as well as the power added
efficiency.
III. ELECTRO-THERMAL CHARACTERISATION
Moreover our pulse-mode test bench allows us to realise
electro-thermal measures (-65°C to +200°C).
We have made measures in pulses of the AlGaN/GaN
2x50µm transistor on SiC substrate from 22°C to 200°C
for a quiescent bias in AB class (Vgs0 = -3.5V,
Vds0 = 24.5V) (Fig. 8).
11th GAAS Symposium - Munich 2003 203
0,00E+00
5,00E-03
1,00E-02
1,50E-02
2,00E-02
2,50E-02
3,00E-02
-8 -6 -4 -2 0 2 4
Vgs (V)
S
ie
m
en
s
0,00E+00
2,00E-02
4,00E-02
6,00E-02
8,00E-02
1,00E-01
1,20E-01
1,40E-01
A
m
p
er
e
Gm @ Tbias+200°C Gm @ Tbias+22°C
Id @ Tbias+200°C Id @ Tbias+22°C
Fig. 8. Evolution of Id and Gm in function of Vgs for
Vdsi=20V at T=Tbias+22°C and at T=Tbias+200°C.
We notice a decrease of the drain current and the
maximum gain when the temperature increases; this is
linked to a decrease of the electrons’ mobility.
We also remark a significant decrease of the maximum
gain when the temperature increases (Fig. 9). Moreover
we notice a decrease of the maximum oscillating
frequency when the temperature increases. On the other
hand, the transition frequency remains almost constant (33
GHz), this is due to the decrease of the gate to source
capacitance versus temperature.
y = 0,002x + 33,067
14
14,5
15
15,5
16
16,5
17
0 50 100 150 200 250
degres (°C)
M
ax
G
ai
n
(d
B
)
0
20
40
60
80
100
120
F
re
q
u
en
ce
(G
H
z)
Max Gain @10GHz Fmax Ft Linéaire (Ft)
Fig. 9. Evolution of the maximum gain @10GHz, of the
maximum oscillating frequency, and the transition
frequency in function of the temperature.
VI. CONCLUSION
In short, throughout this study we can say that, thanks to
(I(V) and [S]) pulse measurements and according to a
specific measuring protocol, we noticed two things
concerning the trapping effects:
- that passivation had a very beneficial effect on
gate-lag effects
- that whatever the nature of the substrate is
(SiC, sapphire, Si), the buffer trapping effects (self-
backgating) are always present.
ACKNOWLEDGEMENT
The authors wish to acknowledge the DGA/STTC
(contract n° 01 34 050 00 470 75 65) for their financial
support, and to TIGER, DAIMLER-CHRYSLER, FBH
for supplying us with various AlGaN/GaN transistors.
REFERENCES
[1] S.T. Sheppard et al., “High-power microwave
GaN/AlGaN HEMT’s on semi-insulating silicon
carbide substrates,” IEEE Electron Devices Letters,
vol. 20, pp161-163, 1999.
[2] S. C. Binari et al, “Trapping effects in GaN and SiC
microwave FETs,” Proceedings of the IEEE, vol. 90,
no. 6, pp. 1048-1058, June 2002.
[3] C. Nguyen et al, “Drain current compression in GaN
MODFETs under large-signal modulation at
microwave frequencies,” Electronics Lett., vol. 35,
no. 16, Aug 1999.
[4] Z. Ouarch et al, “ Measurement Based Non-linear
Electrothermal of GaAs FET with Dynamical
Trapping Effects,” International Microwave
Symposium Digest, IEEE MTT-S, vol. 2, pp. 599-
6002, June 1998.
[5] K. Horio et al, “Two Dimensional Analysis of
Substrate-Trap Effect on Turn-On characteristics in
GaAs MESFETs” IEEE Trans. On Electron.
Devices, vol 47, n°3, pp. 617-624, March 2000.
11th GAAS Symposium - Munich 2003204


Frequency synthesis from 2 to 30 GHz using a 0.35 µm BiCMOS SiGe technology

Crossref

Frequency synthesis from 2 to 30 GHz using a 0.35?m BiCMOS SiGe technology

Electrothermal and trapping effects characterisation ofAlGaN/GaN HEMTsC. Charbonniaud, S. De Meyer, R. Quéré, JP. TeyssierIRCOM, CNRS UMR 6615, University of Limoges, 19100 Brive, FranceAbstract — This paper presents a systematic analysis ofthe two kinds of traps encountered in AlGaN/GaN HEMTs.It is shown that passivation is very efficient to minimize thesurface trap effects but has little effect on the buffer traps.Those ones can only be eliminated through the developmentof high purity substrates. Moreover thermal I-V andmicrowave behaviour of such transmissions is investigatedthrough the use of a pulse-measurement system.I. INTRODUCTIONWide band-gap transistor technologies such asAlGaN/GaN HEMTs are very promising for radiofrequency and microwave power generation [1]. Indeedthey present high breakdown voltages as well as highcurrent densities. Moreover they can also work at hightemperatures. However, parasitic effects induced bytrapping phenomena severely limit the powerperformances of these transistors [2], [3].Pulsed I.V. measurements have demonstrated theirusefulness for characterising such trapping behaviour [4].In this paper we show that two kinds of measurementsallow to discriminate the two kinds of traps that can beencountered in AlGaN/GaN devices: surface traps andbuffer or substrate traps. Effects corresponding to theformer type can be minimised by passivation techniqueswhile the latter are much more difficult to eliminate.Measurements of 2x50 µm AlGaN/GaN transistors grownon various substrates have been carried out and compared.Moreover thermal behaviour of such transistors is ofprime importance due to the high power densities that canbe reached. Temperature dependent pulsed measurementsallow to derive electro-thermal characteristics of thesetransistors.II. TRAPPING EFFECTS CHARACTERISATIONThe trapping effects correspond to the existence ofenergy states which can be occupied by holes or electronsin the gap. These holes or electrons are then maintained inthese levels during an important lapse of time and cannottake part in the conduction, hence the term ‘trap’. Theygenerally result in the presence of impurities or defects inthe crystalline network of the material they are composedof. These phenomena alter the electric behaviour of thetransistor at microwave frequencies.In order to determine the trapping effects thanks to thepulse measurement, we must establish a rigorousmeasuring protocol so as to differentiate the surfacetrapping effects (gate-lag) and the buffer trappings (self-backgating) as accurately as possible. First of all it isnecessary to make sure that the duration of the pulses islower than the emission time constant of the traps. Thuswe chose a pulse duration equivalent to 400 ns with arecurrence equal to 6µs. Finally, to make sure that thedifferences recorded in the measures are those comingfrom trapping effects, we must work with a constanttemperature, hence with a constant dissipated power.The two kinds of ionised traps are figured at Fig. 1.Surface traps results from deep level acceptors that areionised when the gate voltage is set below pinch-off [5].Buffer or substrate traps are localised near the channel andare ionised when an electric field is set up in the channeldirection resulting from a Vds voltage different from zero.Source GateCanal GaNbufferDrainAlGaNFig. 1. Localisation of trap effectsA. Characterisation Of Gate-Lag PhenomenonThe ‘gate-lag’ phenomenon is mainly attributed tosurface trapping effects. To determine these surfacetrapping effects, we make two series of pulsemeasurements with an identical dissipated power(Pdiss = 0W). For that, we choose two quiescent biasesequivalent to (Fig. 2) :Vgs0 = Vp, Vds0 = 0V (1)Vgs0 = 0V, Vds0 = 0V (2)Therefore we can say that in both cases we work with anidentical power equivalent to zero; consequently adifference between both I(V) characteristics implies thepresence of gate-lags.In this case as the quiescent Drain voltage is equal tozero, we can make the assumption that the number ofionised buffer traps is low.11th GAAS Symposium - Munich 2003 201VdsttVgs0=VpVgsiVdsiVds0=0VVgs0=0VVgsFig. 2. Method of measurement to determine the gate-lageffectsWe apply the measurement method described at Fig.2to two AlGaN/GaN 2x50 µm transistors on SiC substrate.The difference between these two transistors is that one ofthem is passivated and the other one is not (Fig. 3). Torealise the measures, we bias the passivated transistor,using two different quiescent biases :Vgs0 = -7V, Vds0 = 0VVgs0 = 0V, Vds0 = 0Vwith a –7V ≤ Vgsi ≤ 2V by step of 1V.Then we bias the second transistor (which has not beenpassivated) with, again, two different quiescent biases :Vgs0 = -3V, Vds0 = 0VVgs0 = 0V, Vds0 = 0Vwith a -3V ≤ Vgsi ≤ 1.5V by step of 0.5V.Consequently we work with Pdiss = 0W.-0.0100.010.020.030.040.050.060.070.080.09-10 0 10 20 30 40 50 60IdenAmperesVds en VoltsVgs0 = -3 V, Vds0 = 0 VVgs0 = 0 V, Vds0 = 0 VSiC substrate without passivation-0.0200.020.040.060.080.10.120.14-10 0 10 20 30 40 50 60IdenAmperesVds en VoltsVgs0 = -7 V, Vds0 = 0 VVgs0 = 0 V, Vds0 = 0 VSiC substrate with passivationa)b)Fig. 3. Output I(V) characteristic for AlGaN/GaN 2x50HEMTs grown on SiC substrate a) with passivationb) without passivationWe can notice that there is a strong decrease of draincurrent on the non-passivated transistor, whereas on thepassivated transistor the output current decreases slightly.However, even in this case of the strong decrease of thedrain current, the knee-voltage of the HEMT is notmodified by the quiescent gate bias.As a consequence, the passivation is a good mean tolimit the gate-lag effects.B. Characterisation Of Self-Backgating PhenomenonJust like the gate-lag phenomenon, the self-backgatingphenomenon manifests itself through slow transienteffects of the drain current , and therefore it creates alimitation of the output current especially for Vds voltagesthat are below the quiescent Drain voltage Vds0. Thiseffect is due to traps in the buffer. The self-backgatingeffects appears when the electrical field between the drainand the source increases suddenly.Indeed, the electrons from the channel are injected in thebuffer and are quickly trapped charging the buffernegatively. Thus this space charge region acts as a back-gate. Consequently in order to maintain the globalneutrality, the electron sheet density in the channeldecreases leading to a decrease of the drain current.Just like before, in order to determine the self-backgating effects, we will make two series of pulsemeasurements with an identical dissipated power equal tozero. To achieve this, we choose two quiescent biasesequal to (Fig. 4) :Vgs0 = Vp, Vds0 = 0V (3)Vgs0 = Vp, Vds0 >> 0V (4)VdsVds0VdsiVds0=0V tVgsVgs0=0VVgsiVgs0=VptFig. 4. Method of measurement to determine the self-backgating effectsWe apply the measurement method described before tothe same passivated transistor that was shown in Fig.3-a.To realize the measures, we bias this transistor, using twodifferent quiescent biases :Vgs0 = -7V, Vds0 = 0VVgs0 = 7V, Vds0 = 25Vwith a –7V ≤ Vgsi ≤ 2V by step of 1V.The quiescent gate bias was set to –7V and thecharacteristic shown in Fig. 5 exhibits a large increase ofthe knee voltage. This shows that despite a goodpassivation, there remains a reduction in the output powerdue to the presence of buffer traps.Indeed applying a large electric field between drain andsource leads to the ionization of a large number of trapsthat are located near the channel. It can be observed thatabove the quiescent drain bias, the characteristics arealmost identical. This fact reveals that the number of11th GAAS Symposium - Munich 2003202ionized traps depends on the maximum value of the biasvoltage Vdsi rather than the average value Vds0 [4].-0.0200.020.040.060.080.10.120.14-10 0 10 20 30 40 50IdenAmperesVds en Volts25Vgs0 = -7 V, Vds0 = 0 VVgs0 = -7 V, Vds0 = 25 V∆ I∆ VFig. 5. Output I(V) characteristic for AlGaN/GaN 2x50HEMTs grown on SiC substrateThis is due to the difference between the capture timeconstant and the emission time constant of the traps.The same experiments have been performed on othertransistors grown on sapphire and Si substrates. Thetransistor grown on sapphire was biased using twodifferent quiescent biases (Fig. 6) :Vgs0 = -5V, Vds0 = 0VVgs0 = 5V, Vds0 = 20Vwith a –5V ≤ Vgsi ≤ 1V by step of 1V,-0.0100.010.020.030.040.050.060.070.080.09-5 0 5 10 15 20 25 30 35 40IdenAmperesVds en Volts20Vgs0 = -5 V, Vds0 = 0 VVgs0 = -5 V, Vds0 = 20 V∆ I∆ VFig. 6. Output I(V) characteristic for AlGaN/GaN 2x50HEMTs grown on Sapphire substrateand the transistor grown on Si was biased in the same waywith (Fig. 7) :Vgs0 = -6V, Vds0 = 0VVgs0 = 6V, Vds0 = 20Vwith a –6V ≤ Vgsi ≤ 2V by step of 1V.-0.0200.020.040.060.080.10.120.14-5 0 5 10 15 20 25 30 35 40 45 50IdenAmperesVds en Volts20Vgs0 = -6 V, Vds0 = 0 VVgs0 = -6 V, Vds0 = 20 V∆ I∆ VFig. 7. Output I(V) characteristic for AlGaN/GaN 2x50HEMTs grown on Si substrateWe can remark that whatever the nature of the substrate,the buffer trapping effects (self-backgating) are verypresent. As a matter of fact, we can see that the draincurrent is really affected by this bias change at dissipatedpower equal to zero.The effects of traps can be evaluated by measuring thedecrease of the maximum available drain current (∆I) andthe increase of the knee-drain voltage (∆V). Thosequantities are evaluated along an ideal load-line thatprovides the maximum of output power in a deep ABclass / B class. Table I summarizes the results obtained.AlGaN/GaN HEMT 2X50SiCsubstrateSapphiresubstrateSisubstrate∆I (mA) 18.33 21.35 10.83∆V (V) 3.24 3.64 1.48TABLE IMEASURES OF VOLTAGE/CURRENT DIFFERENCESDUE TO DRAIN TRAPS ON DIFFERENT SUBSTRATESAs can be noticed from the previous figures, thismodification of the output characteristics strongly affectsthe available output power as well as the power addedefficiency.III. ELECTRO-THERMAL CHARACTERISATIONMoreover our pulse-mode test bench allows us to realiseelectro-thermal measures (-65°C to +200°C).We have made measures in pulses of the AlGaN/GaN2x50µm transistor on SiC substrate from 22°C to 200°Cfor a quiescent bias in AB class (Vgs0 = -3.5V,Vds0 = 24.5V) (Fig. 8).11th GAAS Symposium - Munich 2003 2030,00E+005,00E-031,00E-021,50E-022,00E-022,50E-023,00E-02-8 -6 -4 -2 0 2 4Vgs (V)Siemens0,00E+002,00E-024,00E-026,00E-028,00E-021,00E-011,20E-011,40E-01AmpereGm @ Tbias+200°C Gm @ Tbias+22°CId @ Tbias+200°C Id @ Tbias+22°CFig. 8. Evolution of Id and Gm in function of Vgs forVdsi=20V at T=Tbias+22°C and at T=Tbias+200°C.We notice a decrease of the drain current and themaximum gain when the temperature increases; this islinked to a decrease of the electrons’ mobility.We also remark a significant decrease of the maximumgain when the temperature increases (Fig. 9). Moreoverwe notice a decrease of the maximum oscillatingfrequency when the temperature increases. On the otherhand, the transition frequency remains almost constant (33GHz), this is due to the decrease of the gate to sourcecapacitance versus temperature.y = 0,002x + 33,0671414,51515,51616,5170 50 100 150 200 250degres (°C)MaxGain(dB)020406080100120Frequence(GHz)Max Gain @10GHz Fmax Ft Linéaire (Ft)Fig. 9. Evolution of the maximum gain @10GHz, of themaximum oscillating frequency, and the transitionfrequency in function of the temperature.VI. CONCLUSIONIn short, throughout this study we can say that, thanks to(I(V) and [S]) pulse measurements and according to aspecific measuring protocol, we noticed two thingsconcerning the trapping effects:- that passivation had a very beneficial effect ongate-lag effects- that whatever the nature of the substrate is(SiC, sapphire, Si), the buffer trapping effects (self-backgating) are always present.ACKNOWLEDGEMENTThe authors wish to acknowledge the DGA/STTC(contract n° 01 34 050 00 470 75 65) for their financialsupport, and to TIGER, DAIMLER-CHRYSLER, FBHfor supplying us with various AlGaN/GaN transistors.REFERENCES[1] S.T. Sheppard et al., “High-power microwaveGaN/AlGaN HEMT’s on semi-insulating siliconcarbide substrates,” IEEE Electron Devices Letters,vol. 20, pp161-163, 1999.[2] S. C. Binari et al, “Trapping effects in GaN and SiCmicrowave FETs,” Proceedings of the IEEE, vol. 90,no. 6, pp. 1048-1058, June 2002.[3] C. Nguyen et al, “Drain current compression in GaNMODFETs under large-signal modulation atmicrowave frequencies,” Electronics Lett., vol. 35,no. 16, Aug 1999.[4] Z. Ouarch et al, “ Measurement Based Non-linearElectrothermal of GaAs FET with DynamicalTrapping Effects,” International MicrowaveSymposium Digest, IEEE MTT-S, vol. 2, pp. 599-6002, June 1998.[5] K. Horio et al, “Two Dimensional Analysis ofSubstrate-Trap Effect on Turn-On characteristics inGaAs MESFETs” IEEE Trans. On Electron.Devices, vol 47, n°3, pp. 617-624, March 2000.11th GAAS Symposium - Munich 2003204

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Frequency synthesis from 2 to 30 GHz using a 0.35 µm BiCMOS SiGe technology

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