For the first time, excellent microwave performances including high frequency noise are ported for 0.25 micron gate channel length Fully Depleted (FD) Silicon-on-Insulator (SOI) MOSFET’s: a maximum extrapolated oscillation frequency (fmax) of 70 GHz and the state-of-the-art minimum noise figure (NFmin) of 0.8 dB with high available associated gain (Gass) of 13 dB at 6 GHz, at Vds = 0.75 V, Pdc < 3 mW, have been measured. We demonstrate that the kink related low frequency noise overshoot induced by the floating body effects disappears if the active silicon film thickness is thinned down to 30 nm. Ring oscillators measurements show also that SOI inverters are 30% faster than bulk ones. Finally, the operation at 1.8 V of a sigma delta modulator as well as of critical RF circuits (quadrature generator and mixers) for a zero IF 2 GHz GSM receiver has been demonstrated with this technology

Brut, H.

Compagne, E.

Dambrine, G.

Dessard, V.

Faynot, O.

Flandre, D.

Fletcher, G.

Grouillet, A.

Llinares, P.

Mackowiak, E.

Martin, F.

Pelloie, J.-L.

Picheta, L.

Raskin, J.-P.

Raynaud, C.

Sevenhans, J.

Tabone, C.

Vanhoenacker, D.

Vanmackelberg, M.

English

Pelloie, J.L.

Llnares, P.

HAL Descartes

70 GHz Fmax fully-depleted SOI MOSFET's for low power wireless applications

AMS Acta

70 GHZ FMAX FULLY-DEPLETED SOI MOSFET’S FOR
LOW-POWER WIRELESS APPLICATIONS
C. Raynauda, O. Faynota, J.-L. Pelloiea, C. Tabonea, A. Grouilleta, F. Martina, G. Dambrineb, M.
Vanmackelbergb, L. Pichetab, E. Mackowiakc, H. Brutc, P. Llinaresc, J. Sevenhansd, E. Compagnee,
G. Fletcherf, D. Flandreg, V. Dessardg, D. Vanhoenackerg and J.-P. Rasking
a  Laboratoire d'Electronique de Technologie et d'Instrumentation (LETI), 17 rue des Martyrs, 38054 Grenoble Cedex 9,
France
b  Institut d’Electronique et de Microélectronique du Nord (IEMN), Av. Poincaré, BP 69, 59655 Villeneuve d’Ascq, France
c  ST Microelectronics, 850, rue Jean Monnet, 38926 Crolles Cedex, France
d  ALCATEL Bell Switching Systems Division, F. Wellesplein 1, B-2018 Antwerpen, Belgium
e  DOLPHIN Integration PB 65, ZIRST, 8, chemin des Clos, 38242 Meylan Cedex, France
f  SWINDON Silicon System Ltd, Radnor Street, Swindon, Wiltshire SN1 3PR, United Kingdom
g  Université catholique de Louvain (UCL), Maxwell Building, Place du Levant, 3, B-1348 Louvain la Neuve, Belgium
Abstract - For the first time, excellent microwave
performances including high frequency noise are
reported for 0.25 micron gate channel length Fully
Depleted (FD) Silicon-on-Insulator (SOI) MOSFET’s: a
maximum extrapolated oscillation frequency (fmax) of 70
GHz and the state-of-the-art minimum noise figure
(NFmin) of 0.8 dB with high available associated gain
(Gass) of 13 dB at 6 GHz, at Vds = 0.75 V, Pdc < 3 mW,
have been measured. We demonstrate that the kink
related low frequency noise overshoot induced by the
floating body effects disappears if the active silicon film
thickness is thinned down to 30 nm. Ring oscillators
measurements show also that SOI inverters are 30%
faster than bulk ones. Finally, the operation at 1.8 V of
a sigma delta modulator as well as of critical RF
circuits (quadrature generator and mixers) for a zero
IF 2 GHz GSM receiver has been demonstrated with
this technology.
I. INTRODUCTION
The rapid growth of mobile communication systems leads
an increasing request of low cost and low power mixed
mode integrated circuits. Maturity of Si-based technology
and recent progresses of MOSFET’s microwave
performances, explain Si success against to III-V
technologies for low-power low-voltage wireless
applications [1]-[4]. Silicon-on-Insulator-based MOSFET’s
are very promising devices for multigigahertz applications.
Especially low microwave noise at low drain voltage bias
condition is one of very interesting high frequency
characteristics of such devices. Moreover, due to the
reduction of channel length dimension and the
improvement of electrode processes (silicidation or metal
T-gate processes), very low noise integrated circuits
operating beyond 10 GHz and more are realizable. The
main goal of this paper is to present state-of-the-art low
and high frequency performances of sub-quarter micron
gate length FD and PD SOI MOSFET’s fabricated with a
CMOS-compatible process on low-resistivity (20 Ω.cm)
SIMOX wafers. Accurate knowledge of MOSFET noise
parameters is required in performing realistic and reliable
design of Low Noise Amplifier (LNA), key element of
high sensitive microwave receiver. We have accurately
determined noise parameters of MOSFET’s and we have
evaluated their dependence with the fabrication technology.
Details about the LETI SOI MOSFET’s fabrication process
are given in Section II. Static (Vt versus gate length curves
and on-off drain current characteristics) and low frequency
noise characteristics of FD SOI MOSFET’s are presented
respectively in Sections III and IV. Propagation delay and
DC power consumption of bulk and FD SOI MOSFET’s
are compared in Section V. Microwave performances
including high frequency noise for FD SOI MOSFET’s are
shown in Section VI. Some results obtained for simple RF
functionalities such as a sigma-delta modulator are
presented in Section VII.
II. FULLY-DEPLETED SOI CMOS TECHNOLOGY
200 mm UNIBOND wafers with a 400 nm buried oxide are
used as the starting material. The active silicon film
thickness is thinned down to 40 nm or 30 nm by a
recessed-channel process. Gate oxide of 4.5 nm is grown
after a LOCOS isolation. A field implant is used to
eliminate sidewall leakage. A 200 nm thick polysilicon
layer is deposited and patterned by DUV lithography. A
medium doped drain implant is followed by formation of a
80 nm spacer oxide after which the source-drain regions
are implanted and activated with a 950°C / 15 s RTA. A
titanium salicide process is used to reduce the sheet and
contact resistances of gates and the elevated 80 nm thick
source-drain regions. After the salicide process a gate sheet
resistance of about 10 Ω /,  instead of 100 Ω / for a
classical doped polysilicon gate, is obtained for a 0.25 µm
gate channel length MOSFET. The back-end processing
includes a three level metal process with W plugs and
planarization of intermetal oxides by CMP. Cross-section
of a transistor is presented in Fig. 1.
III. MOSFET’S DC CHARACTERISTICS
Fig. 2 shows the threshold voltage Vt roll-off for both FD
SOI n and p-MOSFET’s. Although Vt is low (about 300
mV at Vds = 0.1 V for 0.25 µm gate length transistors), the
off-current at Vds = 1.8 V is only 6 nA/µm and 1 nA/µm for
0.25 µm n and p-MOSFET’s, respectively. Fig. 3 presents
excellent on-off characteristics (at Vds = 1.8 V) have been
measured although the drive current is limited by high
series resistance due to the thin silicon under the spacer.
IV. LOW FREQUENCY NOISE PARAMETERS
The floating body effect induces a kink related noise
overshoot which adds a Lorentzian spectrum on the flicker
noise. This behavior is clearly shown at Vgs ≈ Vt and Vds = 1
V for devices with a 40 nm active silicon film (tsi). But this
effect disappears if the active silicon film thickness is
thinned down to 30 nm (Fig. 4).
V. PROPAGATION DELAY AND POWER CONSUMPTION
The propagation delay and the power consumption of 90
stages bulk and FD SOI CMOS inverter ring oscillators
(FO = 5, Wn = 5 µm, Wp = 10 µm) are shown in Fig. 5. Due
to the reduction of the total parasitic equivalent capacitance
per gate, the stage delay of the FD SOI inverter is about
30% faster than the bulk one at low power consumption.
VI. HIGH FREQUENCY CHARACTERIZATION
S and noise parameters have been measured using a
HP8510 network analyzer, a HP8971 noise measurement
set-up and tungsten contact Picoprobe microwave probes.
The S-parameters were measured up to 40 GHz and the
noise figures in the 1-18 GHz frequency range. The four
noise parameters are obtained using the NF50 method [5].
A current gain cut-off frequency fT close to 40 GHz at Vgs =
Vds = 1 V has been measured for 0.25 µm FD SOI n-
MOSFET with a current density of 100 mA/mm (see Fig.
6). For the same bias conditions, an extrapolated (from –20
dB/dec slope) maximum oscillation frequency fmax of 70
GHz has been obtained. This result is one of the best
results reported in the literature today for MOSFET’s.
Those high frequency performances are the result of low
capacitances (gate-drain and drain-source capacitances) of
the optimized SOI MOSFET’s structure and the reduced
gate resistance by using the salicide process. Knowing the
3-D physical structure of built MOSFET’s, direct
extraction techniques have been developed to accurately
characterize sub-quarter micron SOI MOSFET’s in the
microwave domain [6]. The characterization procedure is
directly based on the physical meaning of each small-signal
model element. That makes it very useful for controlling
the sensitive fabrication steps such as the silicidation
process of the gate, source and drain regions.
Accurate knowledge of transistor noise parameters is
required in performing realistic and reliable design of Low
Noise Amplifier (LNA), key element of high sensitive
microwave receiver. All the experimental results, presented
in this paragraph, correspond to SOI FD n-MOSFET’s
composed of 12 parallel-connected gate fingers of 0.25 µm
channel length and 6.6 µm width (noted 12x6.6x0.25 µm²).
Fig. 7 shows the variation, at 2 GHz, of the NFmin and Gass
as a function of the drain current density (Vds = 2 V). For a
drain current density close to 60-70 mA/mm, the NFmin is
close to 0.4 dB with Gass of 21 dB. Fig. 8 represents the
state-of-the-art results for different kinds of MOSFET’s
technologies. Low noise microwave performances of FD
SOI MOSFET’s appear to be ones of the best results
reported in the literature. Fig. 9 shows the variation of
NFmin and Gass as a function of drain power density (Vds =
0.75 V) at higher frequency (6 GHz). For a drain power
density close to 25-30 mA/mm, NFmin is about 0.8 dB and
Gass is close to 13 dB. NFmin does not increase too much by
decreasing Vds. These results show that LNA’s could be
designed with a power consumption of less than 35
mW/mm.
VII. ANALOG AND RF CRITICAL BLOCKS FOR A GSM
RECEIVER
The functionality of baseband circuits, including a delta-
sigma modulator (see specifications in Table I) as well as a
quadrature generator (gain and phase accuracy
demonstrated at 2 GHz with a 1.8 V supply voltage) and
mixers has been demonstrated with the FD SOI technology,
without the use of the salicide process (N+ single gate
instead of dual gates). In this case fmax is reduced to about
30 GHz at Vgs = Vds = 0.9 V but these performances are
still sufficient for a 1.8 GHz receiver. Better performances
at lower voltage supply and power consumption can be
expected by using salicided transistors.
VIII. CONCLUSION
We have performed a complete study of low and high
frequency characteristics including noise figures for a 0.25
µm FD SOI MOSFET. These transistors show a NFmin of
about 0.8 dB and a Gass of 13 dB at 6 GHz. Using such
devices, it should be possible to design a LNA with a noise
figure less than 3 dB and 15 dB of gain at 12 GHz. By
decreasing furthermore the gate resistance (by improving
the salicide process or by using a T-gate), such
performances could be obtained at 18 GHz for the same
gate length. Moreover, as performances on digital circuits
show a high speed with a low power consumption
compared to bulk devices, such SOI devices could be used
for wireless applications where high frequency as well as
high speed/low power is required in RF and digital parts,
respectively.
ACKNOWLEDGEMENTS
The authors wish to thank the Microelectronics Department
teams for batch processing and testing. This research has
been partially funded in the frame of an EEC ESPRIT
project.
REFERENCES
[1] C. Raynaud, O. Faynot, J.-L. Pelloie, S. Deleonibus,
D. Vanhoenacker, R. Gillon, J. Sevenhans, E.
Compagne, G. Fletcher and E. Mackowiak, "Fully-
depleted 0.25 µm SOI devices for low power RF
mixed analog-digital circuits", Proceedings 1998
IEEE International SOI Conference, October 1998,
pp. 67-68.
[2] D. D. Rathman, J. A. Burns, R. Berger, A. M. Soares
and R. H. Mathews, "High frequency performance of
a fully depleted 0.25 µm SOI CMOS technology",
1999 IEEE MTT Symposium Digest, June 1999, pp.
577-580.
[3] J. N. Burghartz, M. Hargrove, C. Webster, R. Groves,
M. Keene, K. Jenkins, D. Edelstein, R. Logan and E.
Nowak, "RF potential of a 0.18 µm CMOS logic
technology", 1999 IEEE MTT Symposium Digest,
June 1999.
[4] C. Raynaud, O. Faynot, J.-L. Pelloie, F. Martin, S.
Tedesco, J. Cluzel, A. Grouillet, B. Dal’zotto and D.
Vanhoenacker, "Scability of fully-depleted SOI
technology into 0.13 µm 1.2 V – 1 V CMOS
generation", Proceedings 1999 IEEE International
SOI Conference, October 1998, pp. 86-87.
[5] G. Dambrine, J.-M. Belquin, F. Danneville and A.
Cappy, "A new extrinsic equivalent circuit of
HEMT’s including noise for millimeter-wave circuit
design", IEEE Transactions on Microwave Theory
and Tech., vol. MTT-46, no. 9, pp. 1231-1236, Sept.
1998.
[6] J.P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker, and
J.P. Colinge, "Accurate SOI MOSFET charaterisation
at microwave frequencies for device performance
optimisation and analogue modelling", IEEE
Transactions on Electron Devices, vol. ED-45, no. 5,
pp. 1017-1025, May 1998.
Measured Spec.
Analog Input bandwidth 100 kHz 100 kHz
Analog sampling rate 13/2 MHz 13/2 MHz
Signal/Noise ratio 70-75 dB > 78 dB
Total Harmonic Distorsion 70-85 dB > 40 dB
Power supply 1.6 V-2 V 1.6 V-2 V
Table I. Baseband circuit specifications.
Fig. 1. Cross-section of a salicided 0.25 µm FD SOI
MOSFET.
-0.6 
-0.4 
-0.2 
0 
0.2 
0.4 
0.6 
0.2 0.3 0.4 0.5 0.6 0.7 0.8 
Threshold voltage [V] 
Ldrawn (µm) 
NMOS 
PMOS 
Fig. 2. Vt versus gate length at Vds = 0.1 V.
Fig. 3. On-off characteristics at Vds = 1.8 V.
 
10 -15 
10 -14 
10 -13 
10 -12 
10 -11 
10 1 10 2 10 3 10 4 10 5 
Frequency [Hz] 
Vds = 1 V Vgs ~ Vt 
30 nm 
40 nm 
S v
in
 [
V
2 /
H
z]
 
Fig. 4. LF noise versus frequency at Vgs ≈ Vt, Vds = 1 V;
NMOS, Lg = 0.25 µm, W = 25 µm, tsi = 30 or 40 nm.
 
50 
100 
150 
200 
250 
300 
0 10 20 30 40 P
ro
pa
ga
ti
on
 d
el
ay
 [
ps
/g
at
e]
 
Pd: Idyn/gate.Vdd [µW] 
L = 0.25 µm, FO = 5, 90 gates 
Wn = 5 µm Wp = 10 µm 
Bulk data (from STM) 
in SPACE project 
SOI Fully-Depleted  
1.8 V 
1 V 
1 V 
tsi = 35 nm 
Fig. 5. Propagation delay versus power consumption.
 
10 
20 
30 
40 
50 
60 
70 
80 
10 100 1000 
f T
  a
nd
 f
m
ax
 [
G
H
z]
 
Jds [mA/mm] 
fmax 
fT 
Vds = 1 V 
Fig. 6. fT and fmax versus current density, Vds = 1 V; nxWxLg
= 12x6.6x0.25 µm2.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 100 200 300 400 500
Ids [mA]
N
F
m
in
 [
dB
]
15
20
25
30
G
as
s 
[d
B
]
@ 2 GHz
Fig. 7. FD SOI MOSFET’s evolution of NFmin (V) and Gass
(x) as a function of the drain current density at 2 GHz; Vds
= 2 V; nxWxLg = 12x6.6x0.25 µm².
0
5
10
15
20
25
0 0,5 1 1,5 2 2,5
Minimum Noise Figure [dB]
A
ss
oc
ia
te
d 
G
ai
n 
[d
B
]
MOSFET  >= 0.5 µm
MOSFET "bulk" < 0.2 µm
MOS SOI/SOS >= 0.5µm
SOI 0,25 µm, Salicide
Fig. 8. State-of-the-art high frequency NFmin and Gass for
different published results of MOSFET technologies. Black
dot corresponds to this work.
0.6 
0.8 
1 
1.2 
1.4 
1.6 
1.8 
2 
2.2 
0 
2 
4 
6 
8 
10 
12 
14 
16 
0 50 100 150 200 250 300 350 400 
N
F
m
in
 [
dB
] 
G
as
s [
dB
] 
Pdc [mW/mm] 
NFmin 
Gass 
@ 6 GHz 
Fig. 9. NFmin and Gass versus power consumption at 6 GHz;
Vds = 0.75 V; nxWxLg = 12x6.6x0.25 µm
2.


70 GHZ FMAX fully-depleted SOI MOSFET’S for low-power wireless applications

70 GHZ FMAX FULLY-DEPLETED SOI MOSFET’S FORLOW-POWER WIRELESS APPLICATIONSC. Raynauda, O. Faynota, J.-L. Pelloiea, C. Tabonea, A. Grouilleta, F. Martina, G. Dambrineb, M.Vanmackelbergb, L. Pichetab, E. Mackowiakc, H. Brutc, P. Llinaresc, J. Sevenhansd, E. Compagnee,G. Fletcherf, D. Flandreg, V. Dessardg, D. Vanhoenackerg and J.-P. Raskinga  Laboratoire d'Electronique de Technologie et d'Instrumentation (LETI), 17 rue des Martyrs, 38054 Grenoble Cedex 9,Franceb  Institut d’Electronique et de Microélectronique du Nord (IEMN), Av. Poincaré, BP 69, 59655 Villeneuve d’Ascq, Francec  ST Microelectronics, 850, rue Jean Monnet, 38926 Crolles Cedex, Franced  ALCATEL Bell Switching Systems Division, F. Wellesplein 1, B-2018 Antwerpen, Belgiume  DOLPHIN Integration PB 65, ZIRST, 8, chemin des Clos, 38242 Meylan Cedex, Francef  SWINDON Silicon System Ltd, Radnor Street, Swindon, Wiltshire SN1 3PR, United Kingdomg  Université catholique de Louvain (UCL), Maxwell Building, Place du Levant, 3, B-1348 Louvain la Neuve, BelgiumAbstract - For the first time, excellent microwaveperformances including high frequency noise arereported for 0.25 micron gate channel length FullyDepleted (FD) Silicon-on-Insulator (SOI) MOSFET’s: amaximum extrapolated oscillation frequency (fmax) of 70GHz and the state-of-the-art minimum noise figure(NFmin) of 0.8 dB with high available associated gain(Gass) of 13 dB at 6 GHz, at Vds = 0.75 V, Pdc < 3 mW,have been measured. We demonstrate that the kinkrelated low frequency noise overshoot induced by thefloating body effects disappears if the active silicon filmthickness is thinned down to 30 nm. Ring oscillatorsmeasurements show also that SOI inverters are 30%faster than bulk ones. Finally, the operation at 1.8 V ofa sigma delta modulator as well as of critical RFcircuits (quadrature generator and mixers) for a zeroIF 2 GHz GSM receiver has been demonstrated withthis technology.I. INTRODUCTIONThe rapid growth of mobile communication systems leadsan increasing request of low cost and low power mixedmode integrated circuits. Maturity of Si-based technologyand recent progresses of MOSFET’s microwaveperformances, explain Si success against to III-Vtechnologies for low-power low-voltage wirelessapplications [1]-[4]. Silicon-on-Insulator-based MOSFET’sare very promising devices for multigigahertz applications.Especially low microwave noise at low drain voltage biascondition is one of very interesting high frequencycharacteristics of such devices. Moreover, due to thereduction of channel length dimension and theimprovement of electrode processes (silicidation or metalT-gate processes), very low noise integrated circuitsoperating beyond 10 GHz and more are realizable. Themain goal of this paper is to present state-of-the-art lowand high frequency performances of sub-quarter microngate length FD and PD SOI MOSFET’s fabricated with aCMOS-compatible process on low-resistivity (20 Ω.cm)SIMOX wafers. Accurate knowledge of MOSFET noiseparameters is required in performing realistic and reliabledesign of Low Noise Amplifier (LNA), key element ofhigh sensitive microwave receiver. We have accuratelydetermined noise parameters of MOSFET’s and we haveevaluated their dependence with the fabrication technology.Details about the LETI SOI MOSFET’s fabrication processare given in Section II. Static (Vt versus gate length curvesand on-off drain current characteristics) and low frequencynoise characteristics of FD SOI MOSFET’s are presentedrespectively in Sections III and IV. Propagation delay andDC power consumption of bulk and FD SOI MOSFET’sare compared in Section V. Microwave performancesincluding high frequency noise for FD SOI MOSFET’s areshown in Section VI. Some results obtained for simple RFfunctionalities such as a sigma-delta modulator arepresented in Section VII.II. FULLY-DEPLETED SOI CMOS TECHNOLOGY200 mm UNIBOND wafers with a 400 nm buried oxide areused as the starting material. The active silicon filmthickness is thinned down to 40 nm or 30 nm by arecessed-channel process. Gate oxide of 4.5 nm is grownafter a LOCOS isolation. A field implant is used toeliminate sidewall leakage. A 200 nm thick polysiliconlayer is deposited and patterned by DUV lithography. Amedium doped drain implant is followed by formation of a80 nm spacer oxide after which the source-drain regionsare implanted and activated with a 950°C / 15 s RTA. Atitanium salicide process is used to reduce the sheet andcontact resistances of gates and the elevated 80 nm thicksource-drain regions. After the salicide process a gate sheetresistance of about 10 Ω /,  instead of 100 Ω / for aclassical doped polysilicon gate, is obtained for a 0.25 µmgate channel length MOSFET. The back-end processingincludes a three level metal process with W plugs andplanarization of intermetal oxides by CMP. Cross-sectionof a transistor is presented in Fig. 1.III. MOSFET’S DC CHARACTERISTICSFig. 2 shows the threshold voltage Vt roll-off for both FDSOI n and p-MOSFET’s. Although Vt is low (about 300mV at Vds = 0.1 V for 0.25 µm gate length transistors), theoff-current at Vds = 1.8 V is only 6 nA/µm and 1 nA/µm for0.25 µm n and p-MOSFET’s, respectively. Fig. 3 presentsexcellent on-off characteristics (at Vds = 1.8 V) have beenmeasured although the drive current is limited by highseries resistance due to the thin silicon under the spacer.IV. LOW FREQUENCY NOISE PARAMETERSThe floating body effect induces a kink related noiseovershoot which adds a Lorentzian spectrum on the flickernoise. This behavior is clearly shown at Vgs ≈ Vt and Vds = 1V for devices with a 40 nm active silicon film (tsi). But thiseffect disappears if the active silicon film thickness isthinned down to 30 nm (Fig. 4).V. PROPAGATION DELAY AND POWER CONSUMPTIONThe propagation delay and the power consumption of 90stages bulk and FD SOI CMOS inverter ring oscillators(FO = 5, Wn = 5 µm, Wp = 10 µm) are shown in Fig. 5. Dueto the reduction of the total parasitic equivalent capacitanceper gate, the stage delay of the FD SOI inverter is about30% faster than the bulk one at low power consumption.VI. HIGH FREQUENCY CHARACTERIZATIONS and noise parameters have been measured using aHP8510 network analyzer, a HP8971 noise measurementset-up and tungsten contact Picoprobe microwave probes.The S-parameters were measured up to 40 GHz and thenoise figures in the 1-18 GHz frequency range. The fournoise parameters are obtained using the NF50 method [5].A current gain cut-off frequency fT close to 40 GHz at Vgs =Vds = 1 V has been measured for 0.25 µm FD SOI n-MOSFET with a current density of 100 mA/mm (see Fig.6). For the same bias conditions, an extrapolated (from –20dB/dec slope) maximum oscillation frequency fmax of 70GHz has been obtained. This result is one of the bestresults reported in the literature today for MOSFET’s.Those high frequency performances are the result of lowcapacitances (gate-drain and drain-source capacitances) ofthe optimized SOI MOSFET’s structure and the reducedgate resistance by using the salicide process. Knowing the3-D physical structure of built MOSFET’s, directextraction techniques have been developed to accuratelycharacterize sub-quarter micron SOI MOSFET’s in themicrowave domain [6]. The characterization procedure isdirectly based on the physical meaning of each small-signalmodel element. That makes it very useful for controllingthe sensitive fabrication steps such as the silicidationprocess of the gate, source and drain regions.Accurate knowledge of transistor noise parameters isrequired in performing realistic and reliable design of LowNoise Amplifier (LNA), key element of high sensitivemicrowave receiver. All the experimental results, presentedin this paragraph, correspond to SOI FD n-MOSFET’scomposed of 12 parallel-connected gate fingers of 0.25 µmchannel length and 6.6 µm width (noted 12x6.6x0.25 µm²).Fig. 7 shows the variation, at 2 GHz, of the NFmin and Gassas a function of the drain current density (Vds = 2 V). For adrain current density close to 60-70 mA/mm, the NFmin isclose to 0.4 dB with Gass of 21 dB. Fig. 8 represents thestate-of-the-art results for different kinds of MOSFET’stechnologies. Low noise microwave performances of FDSOI MOSFET’s appear to be ones of the best resultsreported in the literature. Fig. 9 shows the variation ofNFmin and Gass as a function of drain power density (Vds =0.75 V) at higher frequency (6 GHz). For a drain powerdensity close to 25-30 mA/mm, NFmin is about 0.8 dB andGass is close to 13 dB. NFmin does not increase too much bydecreasing Vds. These results show that LNA’s could bedesigned with a power consumption of less than 35mW/mm.VII. ANALOG AND RF CRITICAL BLOCKS FOR A GSMRECEIVERThe functionality of baseband circuits, including a delta-sigma modulator (see specifications in Table I) as well as aquadrature generator (gain and phase accuracydemonstrated at 2 GHz with a 1.8 V supply voltage) andmixers has been demonstrated with the FD SOI technology,without the use of the salicide process (N+ single gateinstead of dual gates). In this case fmax is reduced to about30 GHz at Vgs = Vds = 0.9 V but these performances arestill sufficient for a 1.8 GHz receiver. Better performancesat lower voltage supply and power consumption can beexpected by using salicided transistors.VIII. CONCLUSIONWe have performed a complete study of low and highfrequency characteristics including noise figures for a 0.25µm FD SOI MOSFET. These transistors show a NFmin ofabout 0.8 dB and a Gass of 13 dB at 6 GHz. Using suchdevices, it should be possible to design a LNA with a noisefigure less than 3 dB and 15 dB of gain at 12 GHz. Bydecreasing furthermore the gate resistance (by improvingthe salicide process or by using a T-gate), suchperformances could be obtained at 18 GHz for the samegate length. Moreover, as performances on digital circuitsshow a high speed with a low power consumptioncompared to bulk devices, such SOI devices could be usedfor wireless applications where high frequency as well ashigh speed/low power is required in RF and digital parts,respectively.ACKNOWLEDGEMENTSThe authors wish to thank the Microelectronics Departmentteams for batch processing and testing. This research hasbeen partially funded in the frame of an EEC ESPRITproject.REFERENCES[1] C. Raynaud, O. Faynot, J.-L. Pelloie, S. Deleonibus,D. Vanhoenacker, R. Gillon, J. Sevenhans, E.Compagne, G. Fletcher and E. Mackowiak, "Fully-depleted 0.25 µm SOI devices for low power RFmixed analog-digital circuits", Proceedings 1998IEEE International SOI Conference, October 1998,pp. 67-68.[2] D. D. Rathman, J. A. Burns, R. Berger, A. M. Soaresand R. H. Mathews, "High frequency performance ofa fully depleted 0.25 µm SOI CMOS technology",1999 IEEE MTT Symposium Digest, June 1999, pp.577-580.[3] J. N. Burghartz, M. Hargrove, C. Webster, R. Groves,M. Keene, K. Jenkins, D. Edelstein, R. Logan and E.Nowak, "RF potential of a 0.18 µm CMOS logictechnology", 1999 IEEE MTT Symposium Digest,June 1999.[4] C. Raynaud, O. Faynot, J.-L. Pelloie, F. Martin, S.Tedesco, J. Cluzel, A. Grouillet, B. Dal’zotto and D.Vanhoenacker, "Scability of fully-depleted SOItechnology into 0.13 µm 1.2 V – 1 V CMOSgeneration", Proceedings 1999 IEEE InternationalSOI Conference, October 1998, pp. 86-87.[5] G. Dambrine, J.-M. Belquin, F. Danneville and A.Cappy, "A new extrinsic equivalent circuit ofHEMT’s including noise for millimeter-wave circuitdesign", IEEE Transactions on Microwave Theoryand Tech., vol. MTT-46, no. 9, pp. 1231-1236, Sept.1998.[6] J.P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker, andJ.P. Colinge, "Accurate SOI MOSFET charaterisationat microwave frequencies for device performanceoptimisation and analogue modelling", IEEETransactions on Electron Devices, vol. ED-45, no. 5,pp. 1017-1025, May 1998.Measured Spec.Analog Input bandwidth 100 kHz 100 kHzAnalog sampling rate 13/2 MHz 13/2 MHzSignal/Noise ratio 70-75 dB > 78 dBTotal Harmonic Distorsion 70-85 dB > 40 dBPower supply 1.6 V-2 V 1.6 V-2 VTable I. Baseband circuit specifications.Fig. 1. Cross-section of a salicided 0.25 µm FD SOIMOSFET.-0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Threshold voltage [V] Ldrawn (µm) NMOS PMOS Fig. 2. Vt versus gate length at Vds = 0.1 V.Fig. 3. On-off characteristics at Vds = 1.8 V. 10 -15 10 -14 10 -13 10 -12 10 -11 10 1 10 2 10 3 10 4 10 5 Frequency [Hz] Vds = 1 V Vgs ~ Vt 30 nm 40 nm S vin [V2 /Hz] Fig. 4. LF noise versus frequency at Vgs ≈ Vt, Vds = 1 V;NMOS, Lg = 0.25 µm, W = 25 µm, tsi = 30 or 40 nm. 50 100 150 200 250 300 0 10 20 30 40 Propagation delay [ps/gate] Pd: Idyn/gate.Vdd [µW] L = 0.25 µm, FO = 5, 90 gates Wn = 5 µm Wp = 10 µm Bulk data (from STM) in SPACE project SOI Fully-Depleted  1.8 V 1 V 1 V tsi = 35 nm Fig. 5. Propagation delay versus power consumption. 10 20 30 40 50 60 70 80 10 100 1000 f T  and f max [GHz] Jds [mA/mm] fmax fT Vds = 1 V Fig. 6. fT and fmax versus current density, Vds = 1 V; nxWxLg= 12x6.6x0.25 µm2.00.10.20.30.40.50.60.70 100 200 300 400 500Ids [mA]NFmin [dB]15202530Gass [dB]@ 2 GHzFig. 7. FD SOI MOSFET’s evolution of NFmin (V) and Gass(x) as a function of the drain current density at 2 GHz; Vds= 2 V; nxWxLg = 12x6.6x0.25 µm².05101520250 0,5 1 1,5 2 2,5Minimum Noise Figure [dB]Associated Gain [dB]MOSFET  >= 0.5 µmMOSFET "bulk" < 0.2 µmMOS SOI/SOS >= 0.5µmSOI 0,25 µm, SalicideFig. 8. State-of-the-art high frequency NFmin and Gass fordifferent published results of MOSFET technologies. Blackdot corresponds to this work.0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 0 2 4 6 8 10 12 14 16 0 50 100 150 200 250 300 350 400 NF min [dB] Gass [dB] Pdc [mW/mm] NFmin Gass @ 6 GHz Fig. 9. NFmin and Gass versus power consumption at 6 GHz;Vds = 0.75 V; nxWxLg = 12x6.6x0.25 µm2.

AMS Acta - Alm@DL - Università di Bologna

70 GHZ FMAX FULLY-DEPLETED SOI MOSFET’S FOR
LOW-POWER WIRELESS APPLICATIONS
C. Raynauda, O. Faynota, J.-L. Pelloiea, C. Tabonea, A. Grouilleta, F. Martina, G. Dambrineb, M.
Vanmackelbergb, L. Pichetab, E. Mackowiakc, H. Brutc, P. Llinaresc, J. Sevenhansd, E. Compagnee,
G. Fletcherf, D. Flandreg, V. Dessardg, D. Vanhoenackerg and J.-P. Rasking
a 
 Laboratoire d'Electronique de Technologie et d'Instrumentation (LETI), 17 rue des Martyrs, 38054 Grenoble Cedex 9,
France
b 
 Institut d’Electronique et de Microélectronique du Nord (IEMN), Av. Poincaré, BP 69, 59655 Villeneuve d’Ascq, France
c 
 ST Microelectronics, 850, rue Jean Monnet, 38926 Crolles Cedex, France
d 
 ALCATEL Bell Switching Systems Division, F. Wellesplein 1, B-2018 Antwerpen, Belgium
e 
 DOLPHIN Integration PB 65, ZIRST, 8, chemin des Clos, 38242 Meylan Cedex, France
f 
 SWINDON Silicon System Ltd, Radnor Street, Swindon, Wiltshire SN1 3PR, United Kingdom
g 
 Université catholique de Louvain (UCL), Maxwell Building, Place du Levant, 3, B-1348 Louvain la Neuve, Belgium
Abstract -
 For the first time, excellent microwave
performances including high frequency noise are
reported for 0.25 micron gate channel length Fully
Depleted (FD) Silicon-on-Insulator (SOI) MOSFET’s: a
maximum extrapolated oscillation frequency (fmax) of 70
GHz and the state-of-the-art minimum noise figure
(NFmin) of 0.8 dB with high available associated gain
(Gass) of 13 dB at 6 GHz, at Vds = 0.75 V, Pdc < 3 mW,
have been measured. We demonstrate that the kink
related low frequency noise overshoot induced by the
floating body effects disappears if the active silicon film
thickness is thinned down to 30 nm. Ring oscillators
measurements show also that SOI inverters are 30%
faster than bulk ones. Finally, the operation at 1.8 V of
a sigma delta modulator as well as of critical RF
circuits (quadrature generator and mixers) for a zero
IF 2 GHz GSM receiver has been demonstrated with
this technology.
I. INTRODUCTION
The rapid growth of mobile communication systems leads
an increasing request of low cost and low power mixed
mode integrated circuits. Maturity of Si-based technology
and recent progresses of MOSFET’s microwave
performances, explain Si success against to III-V
technologies for low-power low-voltage wireless
applications [1]-[4]. Silicon-on-Insulator-based MOSFET’s
are very promising devices for multigigahertz applications.
Especially low microwave noise at low drain voltage bias
condition is one of very interesting high frequency
characteristics of such devices. Moreover, due to the
reduction of channel length dimension and the
improvement of electrode processes (silicidation or metal
T-gate processes), very low noise integrated circuits
operating beyond 10 GHz and more are realizable. The
main goal of this paper is to present state-of-the-art low
and high frequency performances of sub-quarter micron
gate length FD and PD SOI MOSFET’s fabricated with a
CMOS-compatible process on low-resistivity (20 Ω.cm)
SIMOX wafers. Accurate knowledge of MOSFET noise
parameters is required in performing realistic and reliable
design of Low Noise Amplifier (LNA), key element of
high sensitive microwave receiver. We have accurately
determined noise parameters of MOSFET’s and we have
evaluated their dependence with the fabrication technology.
Details about the LETI SOI MOSFET’s fabrication process
are given in Section II. Static (Vt versus gate length curves
and on-off drain current characteristics) and low frequency
noise characteristics of FD SOI MOSFET’s are presented
respectively in Sections III and IV. Propagation delay and
DC power consumption of bulk and FD SOI MOSFET’s
are compared in Section V. Microwave performances
including high frequency noise for FD SOI MOSFET’s are
shown in Section VI. Some results obtained for simple RF
functionalities such as a sigma-delta modulator are
presented in Section VII.
II. FULLY-DEPLETED SOI CMOS TECHNOLOGY
200 mm UNIBOND wafers with a 400 nm buried oxide are
used as the starting material. The active silicon film
thickness is thinned down to 40 nm or 30 nm by a
recessed-channel process. Gate oxide of 4.5 nm is grown
after a LOCOS isolation. A field implant is used to
eliminate sidewall leakage. A 200 nm thick polysilicon
layer is deposited and patterned by DUV lithography. A
medium doped drain implant is followed by formation of a
80 nm spacer oxide after which the source-drain regions
are implanted and activated with a 950°C / 15 s RTA. A
titanium salicide process is used to reduce the sheet and
contact resistances of gates and the elevated 80 nm thick
source-drain regions. After the salicide process a gate sheet
resistance of about 10 Ω /,  instead of 100 Ω / for a
classical doped polysilicon gate, is obtained for a 0.25 µm
gate channel length MOSFET. The back-end processing
includes a three level metal process with W plugs and
planarization of intermetal oxides by CMP. Cross-section
of a transistor is presented in Fig. 1.
III. MOSFET’S DC CHARACTERISTICS
Fig. 2 shows the threshold voltage Vt roll-off for both FD
SOI n and p-MOSFET’s. Although Vt is low (about 300
mV at Vds = 0.1 V for 0.25 µm gate length transistors), the
off-current at Vds = 1.8 V is only 6 nA/µm and 1 nA/µm for
0.25 µm n and p-MOSFET’s, respectively. Fig. 3 presents
excellent on-off characteristics (at Vds = 1.8 V) have been
measured although the drive current is limited by high
series resistance due to the thin silicon under the spacer.
IV. LOW FREQUENCY NOISE PARAMETERS
The floating body effect induces a kink related noise
overshoot which adds a Lorentzian spectrum on the flicker
noise. This behavior is clearly shown at Vgs ≈ Vt and Vds = 1
V for devices with a 40 nm active silicon film (tsi). But this
effect disappears if the active silicon film thickness is
thinned down to 30 nm (Fig. 4).
V. PROPAGATION DELAY AND POWER CONSUMPTION
The propagation delay and the power consumption of 90
stages bulk and FD SOI CMOS inverter ring oscillators
(FO = 5, Wn = 5 µm, Wp = 10 µm) are shown in Fig. 5. Due
to the reduction of the total parasitic equivalent capacitance
per gate, the stage delay of the FD SOI inverter is about
30% faster than the bulk one at low power consumption.
VI. HIGH FREQUENCY CHARACTERIZATION
S and noise parameters have been measured using a
HP8510 network analyzer, a HP8971 noise measurement
set-up and tungsten contact Picoprobe microwave probes.
The S-parameters were measured up to 40 GHz and the
noise figures in the 1-18 GHz frequency range. The four
noise parameters are obtained using the NF50 method [5].
A current gain cut-off frequency fT close to 40 GHz at Vgs =
Vds = 1 V has been measured for 0.25 µm FD SOI n-
MOSFET with a current density of 100 mA/mm (see Fig.
6). For the same bias conditions, an extrapolated (from –20
dB/dec slope) maximum oscillation frequency fmax of 70
GHz has been obtained. This result is one of the best
results reported in the literature today for MOSFET’s.
Those high frequency performances are the result of low
capacitances (gate-drain and drain-source capacitances) of
the optimized SOI MOSFET’s structure and the reduced
gate resistance by using the salicide process. Knowing the
3-D physical structure of built MOSFET’s, direct
extraction techniques have been developed to accurately
characterize sub-quarter micron SOI MOSFET’s in the
microwave domain [6]. The characterization procedure is
directly based on the physical meaning of each small-signal
model element. That makes it very useful for controlling
the sensitive fabrication steps such as the silicidation
process of the gate, source and drain regions.
Accurate knowledge of transistor noise parameters is
required in performing realistic and reliable design of Low
Noise Amplifier (LNA), key element of high sensitive
microwave receiver. All the experimental results, presented
in this paragraph, correspond to SOI FD n-MOSFET’s
composed of 12 parallel-connected gate fingers of 0.25 µm
channel length and 6.6 µm width (noted 12x6.6x0.25 µm²).
Fig. 7 shows the variation, at 2 GHz, of the NFmin and Gass
as a function of the drain current density (Vds = 2 V). For a
drain current density close to 60-70 mA/mm, the NFmin is
close to 0.4 dB with Gass of 21 dB. Fig. 8 represents the
state-of-the-art results for different kinds of MOSFET’s
technologies. Low noise microwave performances of FD
SOI MOSFET’s appear to be ones of the best results
reported in the literature. Fig. 9 shows the variation of
NFmin and Gass as a function of drain power density (Vds =
0.75 V) at higher frequency (6 GHz). For a drain power
density close to 25-30 mA/mm, NFmin is about 0.8 dB and
Gass is close to 13 dB. NFmin does not increase too much by
decreasing Vds. These results show that LNA’s could be
designed with a power consumption of less than 35
mW/mm.
VII. ANALOG AND RF CRITICAL BLOCKS FOR A GSM
RECEIVER
The functionality of baseband circuits, including a delta-
sigma modulator (see specifications in Table I) as well as a
quadrature generator (gain and phase accuracy
demonstrated at 2 GHz with a 1.8 V supply voltage) and
mixers has been demonstrated with the FD SOI technology,
without the use of the salicide process (N+ single gate
instead of dual gates). In this case fmax is reduced to about
30 GHz at Vgs = Vds = 0.9 V but these performances are
still sufficient for a 1.8 GHz receiver. Better performances
at lower voltage supply and power consumption can be
expected by using salicided transistors.
VIII. CONCLUSION
We have performed a complete study of low and high
frequency characteristics including noise figures for a 0.25
µm FD SOI MOSFET. These transistors show a NFmin of
about 0.8 dB and a Gass of 13 dB at 6 GHz. Using such
devices, it should be possible to design a LNA with a noise
figure less than 3 dB and 15 dB of gain at 12 GHz. By
decreasing furthermore the gate resistance (by improving
the salicide process or by using a T-gate), such
performances could be obtained at 18 GHz for the same
gate length. Moreover, as performances on digital circuits
show a high speed with a low power consumption
compared to bulk devices, such SOI devices could be used
for wireless applications where high frequency as well as
high speed/low power is required in RF and digital parts,
respectively.
ACKNOWLEDGEMENTS
The authors wish to thank the Microelectronics Department
teams for batch processing and testing. This research has
been partially funded in the frame of an EEC ESPRIT
project.
REFERENCES
[1] C. Raynaud, O. Faynot, J.-L. Pelloie, S. Deleonibus,
D. Vanhoenacker, R. Gillon, J. Sevenhans, E.
Compagne, G. Fletcher and E. Mackowiak, "Fully-
depleted 0.25 µm SOI devices for low power RF
mixed analog-digital circuits", Proceedings 1998
IEEE International SOI Conference, October 1998,
pp. 67-68.
[2] D. D. Rathman, J. A. Burns, R. Berger, A. M. Soares
and R. H. Mathews, "High frequency performance of
a fully depleted 0.25 µm SOI CMOS technology",
1999 IEEE MTT Symposium Digest, June 1999, pp.
577-580.
[3] J. N. Burghartz, M. Hargrove, C. Webster, R. Groves,
M. Keene, K. Jenkins, D. Edelstein, R. Logan and E.
Nowak, "RF potential of a 0.18 µm CMOS logic
technology", 1999 IEEE MTT Symposium Digest,
June 1999.
[4] C. Raynaud, O. Faynot, J.-L. Pelloie, F. Martin, S.
Tedesco, J. Cluzel, A. Grouillet, B. Dal’zotto and D.
Vanhoenacker, "Scability of fully-depleted SOI
technology into 0.13 µm 1.2 V – 1 V CMOS
generation", Proceedings 1999 IEEE International
SOI Conference, October 1998, pp. 86-87.
[5] G. Dambrine, J.-M. Belquin, F. Danneville and A.
Cappy, "A new extrinsic equivalent circuit of
HEMT’s including noise for millimeter-wave circuit
design", IEEE Transactions on Microwave Theory
and Tech., vol. MTT-46, no. 9, pp. 1231-1236, Sept.
1998.
[6] J.P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker, and
J.P. Colinge, "Accurate SOI MOSFET charaterisation
at microwave frequencies for device performance
optimisation and analogue modelling", IEEE
Transactions on Electron Devices, vol. ED-45, no. 5,
pp. 1017-1025, May 1998.
Measured Spec.
Analog Input bandwidth 100 kHz 100 kHz
Analog sampling rate 13/2 MHz 13/2 MHz
Signal/Noise ratio 70-75 dB > 78 dB
Total Harmonic Distorsion 70-85 dB > 40 dB
Power supply 1.6 V-2 V 1.6 V-2 V
Table I. Baseband circuit specifications.
Fig. 1. Cross-section of a salicided 0.25 µm FD SOI
MOSFET.
-0.6 
-0.4 
-0.2 
0 
0.2 
0.4 
0.6 
0.2
 
0.3
 
0.4
 
0.5
 
0.6
 
0.7
 
0.8
 
Threshold voltage [V] 
Ldrawn (µm) 
NMOS 
PMOS 
Fig. 2. Vt versus gate length at Vds = 0.1 V.
Fig. 3. On-off characteristics at Vds = 1.8 V.
 10 -15 
10 -14 
10 -13 
10 -12 
10 -11 
10 1 10 2 10 3 10 4 10 5 
Frequency [Hz] 
Vds = 1 V Vgs ~ Vt 
30 nm 
40 nm 
S v
in
 
[V
2 /H
z] 
Fig. 4. LF noise versus frequency at Vgs ≈ Vt, Vds = 1 V;
NMOS, Lg = 0.25 µm, W = 25 µm, tsi = 30 or 40 nm.
 
50 
100 
150 
200 
250 
300 
0 10 20 30 40 P
ro
pa
ga
tio
n
 
de
la
y 
[p
s/g
at
e] 
Pd: Idyn/gate.Vdd [µW] 
L = 0.25 µm, FO = 5, 90 gates 
Wn = 5 µm Wp = 10 µm 
Bulk data (from STM) 
in SPACE project 
SOI Fully-Depleted  
1.8 V 
1 V 
1 V 
tsi = 35 nm 
Fig. 5. Propagation delay versus power consumption.
 
10 
20 
30 
40 
50 
60 
70 
80 
10 100 1000 
f T
 
 
a
n
d 
f m
ax
 
[G
Hz
] 
Jds [mA/mm] 
fmax 
fT 
Vds = 1 V 
Fig. 6. fT and fmax versus current density, Vds = 1 V; nxWxLg
= 12x6.6x0.25 µm2.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 100 200 300 400 500
Ids [mA]
N
Fm
in
 [d
B]
15
20
25
30
G
as
s [
dB
]
@ 2 GHz
Fig. 7. FD SOI MOSFET’s evolution of NFmin (V) and Gass
(x) as a function of the drain current density at 2 GHz; Vds
= 2 V; nxWxLg = 12x6.6x0.25 µm².
0
5
10
15
20
25
0 0,5 1 1,5 2 2,5
Minimum Noise Figure [dB]
A
ss
oc
ia
te
d 
G
ai
n 
[d
B]
MOSFET  >= 0.5 µm
MOSFET "bulk" < 0.2 µm
MOS SOI/SOS >= 0.5µm
SOI 0,25 µm, Salicide
Fig. 8. State-of-the-art high frequency NFmin and Gass for
different published results of MOSFET technologies. Black
dot corresponds to this work.
0.6 
0.8 
1 
1.2 
1.4 
1.6 
1.8 
2 
2.2 
0 
2 
4 
6 
8 
10 
12 
14 
16 
0 50 100 150 200 250 300 350 400 
N
F m
in
 
[d
B]
 
G
as
s 
[d
B]
 
Pdc [mW/mm] 
NFmin 
Gass 
@ 6 GHz 
Fig. 9. NFmin and Gass versus power consumption at 6 GHz;
Vds = 0.75 V; nxWxLg = 12x6.6x0.25 µm2.


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70 GHZ FMAX fully-depleted SOI MOSFET’S for low-power wireless applications

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