In this thesis an RF Class-D Power Amplifier is presented. The analysis of the Class-D
amplifier considering ideal components has shown that the drain efficiency of 100% can
be achieved. The output power and the drain efficiency are degraded by the internal
resistance of each component. A driver is used to drive the gate capacitances of the Class-D amplifier. Both driver and amplifier are implemented with CMOS inverters. The size of the inverters in the driver is scaled down by a factor of 3 relatively to the preceding stage.
The first being the inverter of the Class-D amplifier. At the output a 3rd order Butterworth bandpass filter is implemented. A non-ideal analysis of the Class-D amplifier is performed to create a base model which is used to aid in the design of the circuit.
The RF Class-D Power Amplifier with the operation frequency of 2.4GHz was implemented with standard 130 nm CMOS technology. Two simulations were taken into
account considering ideal and pre-layout components in the output filter. The following
results were obtained when using ideal components: the output power of 6.91 dBm, the
drain efficiency of 40% and the overall efficiency of 23%. Using pre-layout components the results were the following: the output power of 0.317 dBm the drain and overall efficiency of 8.6% and 4.9%, respectively
