Assessment of III-V FinFETs at 20nm Node: A Process Variation Analysis

Abstract

AbstractThe endless miniaturization of Si based MOSFETs has the key for driving the electronic revolution. However, scaling of the channel length is the enormous challenge to preserve the performance in terms of speed, power and electrostatic integrity at each technology nodes. Subsequently all researchers have been analyzing new device materials and architectures to fix this challenge. After continuous development in the areas of devices and materials have lastly conveyed III-V MOSFETs with high channel mobility. This paper is a discussion about the impact of fin height (HFin) and fin width (WFin) of a GaAs-FinFET, which affect the reliability of the device in view of various performance measures. A detailed analysis about the impact of geometry parameters like (HFin) and (WFin) on the static or low frequency performances like threshold voltage (Vth), on-off ratio (Ion/Ioff), power dissipation, subthreshold slope (SS), transconductance (gm), early voltage (VEA), gain (AV) and dynamic or high frequency performances as gate capacitance (Cgg), cut-off frequency (fT), delay (CV/I), energy (CV2), energy delay product (EDP) are systematically presented