'Institute of Electrical and Electronics Engineers (IEEE)'
Doi
Abstract
This paper proposes the design of hierarchical piecewise-affine (PWA) controllers to alleviate the processing time or prohibitive memory requirements of large controller structures. The constituent PWA modules of the hierarchical solution have fewer inputs and/or coarser partitions, so that they can reduce considerably the hardware resources required and/or the time response of the controller. A design methodology aided by CAD tools is employed to design the parameters of the controller, implement its architecture in an FPGA, and verify the static and dynamic behavior of the digital implementation by applying hardware-in-the-loop testing.Comunidad Europea FP7-IST-248858Ministerio de Ciencia e Innovación TEC2008-04920 y DPI2008-03847Junta de Andalucía P08-TIC-0367
