Nowadays, verification of digital integrated circuit has been
focused more and more from the timing and area field to current and
power estimations. The main problem with this kind of verification is
on the lack of precision of current estimations when working at higher
levels (logic, RT, architectural levels). To solve this problem it is not only
necessary to use good current models for switching activity but, also, it
is necessary to calculate this switching activity with high accuracy. In
this paper we present an alternative to estimate current consumption
using logic-level simulation. To do that, we use a simple but accurate
enough current model to calculate the current consumption for each signal
transition, and a delay model that obtains high accuracy when it is
used to measure the switching activity (the Degradation Delay Model
-DDM-). In the paper we present the current model for CMOS inverter,
the characterization process and the model implementation in the logic
simulator HALOTIS that includes the DDM. Results show a high accuracy
in the estimation of current curves when compared to HSPICE, and
a potentially large improvement over conventional approaches.MEC META TEC 2004-00840/MI
