Timing verification of digital CMOS circuits is a
key point in the design process. In this contribution we present
the extension to gates of the Inertial and Degradation Delay
Model for logic timing simulation which is able to take account
of the propagation of arbitrarily narrow pulses. As a result, the
model is ready to be applied to the simulation and verification
of complex circuits. Simulation results show an accuracy similar
to HSPICE and greatly improved precision over conventional
delay models.Ministerio de Ciencia y Tecnología TIC 2000-135

Acosta Jiménez, Antonio José

Bellido Díaz, Manuel Jesús

Juan Chico, Jorge

Ruiz de Clavijo Vázquez, Paulino

Valencia Barrero, Manuel

idUS. Depósito de Investigación Universidad de Sevilla

GATE-LEVEL SIMULATION OF CMOS CIRCUITS USING THE IDDM MODEL out ini T M. J. Bellido *, J. Juan-Chico *, R Ruiz de Clavijo *, A. J. Acosta **, M. Valencia * 1.. Instituto de Microelectronica de Sevilla-CNM, Avda. Reina Mercedes s/n, 41012 Sevilla, Spain :':also with Departamento de Tecnologia Electronica (Univ. de Sevilla) *Wso  with Departamento de Electronica y Electromagnetismo (Univ. de Sevilla) e-mail: bellido@imse.cnm.es Abstract.- Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is able to take account of the propagation of arbitrarily narrow pulses. As a result, the model is ready to be applied to the simulation and verification of complex circuits. Simulation results show an accuracy sim- ilar to HSPICE and greatly improved precision over conven- tional delay models. 1. INTRODUCTION As digital circuits become larger and faster, better analysis tools are required in order to achieve a successful design pro- cess. Simulation of larger circuits is aided by the evolution of computer systems which performance has been evolving quickly for years. In the field of logic simulation of digital CMOS circuits, delay models exist that take into account most issues affecting accuracy [ I  .2,3,4]: low voltage, submicron and deep submicron devices, transition waveform, etc. There are also dynamic effects, the most important being the so- called i n p t  collisions [5] ,  which happens when two or more input signals change almost simultaneously. The type of input collision that more notably affects the behavior of digital cir- cuits are the glitch collisions, or those that may cause narrow pulses or glitches. This is also strongly related to the modeling of the inertial effect [6] which determines when a glitch is fil- tered. In previous papers [7, 8.91 we have presented a very ac- curate model for the CMOS inverter that handles the generation and propagation of glitches. which makes an impor- tant headway in logic timing simulation. This model is called Iriertial and Degradation Delay Model (IDDM). In the present paper we extent the model to simple gates (<N>AND, <N>OR) from the viewpoint of a gate-level mod- eling, looking for an external characterization suited to the simulation of circuit made out of standard cell. In Sect. 2 we summarize the basic aspects of the IDDM. In Sect. 3, will This work has been partially supported by the MCYT of the Spanish Government under project TIC 2000- 1350. inj n ini. 7 . .  . out ,(a> Fig. 1 .  Quantification of delay degradation: a) degradation due to a narrow pulse, b) degradation due to a glitch collision. make the extension to gates, studying the types of glitch colli- sions and defining the IDDM at the gate level. To verify the ac- curacy of the model a 4x4 multiplier is simulated using the model in Sect. 4. Finally. we derive some conclusions. 2. INERTIAL AND DEGRADATION DELAY MODEL (IDDM) The degradation effect consists in the reduction of the propa- gation delay of an input transition to a gate, when this input transition takes place close in time to a previous input transi- tion. This effect includes the propagation of narrow pulses and fast pulse trains, and the delay produced by glitch collisions. This reduction in the delay can be expressed with an attenuat- ing factor applied to the normalpropagation delay, t p O  , which is the delay for a single, isolated transition without taking ac- count of the degradation effect: T - T  ( -0) t p  = t p O ( l - e  where Tis the time elapsed since the last output transition, and determines how much degradation applies to the current tran- sition, and T o  and z are the degradation parameters, which are determined by fitting to electrical simulation data. For a given input transition, degradation will depend on the value of T, which express the internal state of the gate caused by previ- ous transitions when a new transition arrives (Fig. 1). Parame- ters tpO , To  and z , in turn, depend on multiple factors: input transition time ( til2 ), output load ( C, ), supply voltage ( Y,, ) and gate's geometry ( W, and W, ). For the normal propaga- tion delay, tpO ,good models can be found in the literature [ 1, 21 and any of them can be used here. In [8] we obtained expres- sions for To and T as a function of these parameters: V-483 0-7803-668.5-910 1 /$10.0002001 IEEE "where the pair (x, y) is (f, N) or (I-, P )  to distinguish falling from rising output transitions respectively. VTN and V ,  are the MOS transistors thresholds. The parameters a, 1? and c are ob- tained in order to fit simulation data and characterize the fabri- cation process. Glitch degradation should be combined with inertial effect because, after sucesive degradations, a runt pulse will be eliminated. In [SI we have demonstrated that the con- ventional model for inertial effect, defined as an inertial delay, may produce wrong results in a logic simulation. In that work we proposed a new treatment for the inertial effect, that togeth- er with the DDM model results in the IDDM model: Inertial and Degradation Delay Model. Basically, we proposed to pro- vide every input with a new parameter V ,  that is the voltage threshold associated to the gate input. An input pulse is propa- gated only if it crosses the V,  value. Type of collision 3. INERTIAL AND DEGRADATION DELAY MODEL AT THE GATE LEVEL In this section we will extent the IDDM to simple gates (<N>AND, <N>OR) by performing three steps: 1 .  Reformulate (2) at the gate level, when no information about the gate's internal structure is available. Gate-level degradation parameters are defined in this step. 2. Define a IDDM exhaustive model that allow us to calcu- late the parameter's values for each glitch collision that causes degradation. 3. From the analysis of the parameter's values obtained above, we will define an IDDM simplified model that reduces significantly the total number of parameters but keeps the accuracy of the model. 3.1. IDDM reformulation at the gate level and exhaustive model To rewrite (2) we join together in new gate-level parameters the old ones and those inrernal parameters, not visible at the gate level. In other words, a becomes A , b,/ W I ,  becomes B and c, V,,, becomes C . In this way, ( 2 )  is rewritten as Input evolution Final output transition NAND NOR I NAND NOR I z V,, = A + BC, To = (i - cD)Tir7 C (3) Type ' A gives the value of z when C, = 0 ,  and is strongly related to the gate's internal output capacitance: B depends on the ge- ometry (or equivalent geometry) of the gate and C is related to some "effective" gate threshold. A single value of A, B and C will be calculated for each glitch collision. In a simple gate we can distinguish between two types of glitch collisions, depending on how and to which values in'puts change. In the following we will consider the NAND I i: 0-1-0 i: 1-0-1 rising falling rest: o rest: 1 (0 ( f )  gate case since a similar discussion can be applied to the NOR gate and the non-inverting AND, OR gates. Two types of glitch collisions can be defined: Type 1: Initially, all inputs have value 1 and the output is 0. The output nzav change if any input changes, and a glitch may occur only if the same input changes again to value 1. Only one input is involved in this type of glitch collision and then, n possible collisions of type 1 exist for a n-input simple gate. Type 2: In this case. every input except one (thej-th) have value 1 and the output is also 1. The output niay change only if inputj changes to 1, and an output glitch may occur if any input (the i-th) changes to 0. Any input pair may produce a glitch collision of type 2, resulting in 17? possi- bilities. We use collision4 to refer to type-I collisions with i-th input changing, and collision-ij to refer to a type-' collision with input i-th changing after input j-th. In Table 1 we have sum- marized the properties of both types of collisions for NOR and NAND gates. The total number of collisions for a n-input gate including type-I and type-' is 12 + n2 = ~ ( 1 2  + 1) .  Any of such colli- sions may be studied like an inverter under a narrow pulse in- put. Equations (1) and (3) can be applied to each case and a particular set of (A, B, C) parameters obtained for each colli- sion. Thus, a n-input gate has 3n(rz + 1 ) degradation parame- ters. This is the IDDM exhaustive model. In Table 2 we show the parameters for gates NOR2, NAND2 and INVERTER in a vectodmatrix form. The expressions in (3) can also be written in vector/matrix form: - -  - -  ?,.V,, = A,. + B,.CL Z f V , ,  = A f + B f C L  Type 2 where f i l l  are n-dimensional all-1's vector or matrix depend-. ing on the gate. 3.2. IDDM simplified model To obtain the whole set of parameter for a gate we use a char- j :  1-0 j :  0-1 i: 0-1 i: 1-0 rest: 0 rest: I falling rising (f) ( r )  V-484 Table 2: Vector/matrix form of gate-level degradation parameter for an INVETER and two-inputs NOR and NAND gates. 1 Gate 1 ParameterA Parameter B Parameter C Table 4: Vector form of simplified gate-level degradation parameter for a four-inputs NOR and NAND gates. NAND4 By E,. 7.211 7.455 7.564 7.609 i,. 14.50 15.42 15.76 16.24 1.563 1.470 1.397 1.299 e,f 1.497 1.397 1.270 1.049 1.767 2.099 2.375 2.706 E,. 1.898 2.431 2.907 3.203 It means that in practice, the degradation effect does not depend on which input triggered the last output transition, it depends on the state of the gate, but not on which input put the gate on that state. This makes that degradation parameters of the form Asjj to be very similar for different values of j ,  being any of A, B or c and s, we propose a siinpliJ5ed degradation model for gates. in which we consider a single value of the parameter regardless the value of j .  It means substituting each row in the matrices of Table 3 for a single value. This way, each matrix in Table 3 is reduced to a single column, which can be written like a vector. The resulting simplified set of parameter for NOR4 and NAND4 gates of the previous example are shown in Table 4. The num- ber of glitch collisions that we need to take into account is reduced to 2 n .  The values of the parameter for different j are so s'imilar that the simplified model is almost as accurate as the exhaustive model, but the number of parameters is greatly reduced, as well as the characterization process complexity. only on when that output transition took place. In other words, INV B,. = B,, c,. = c,. Table 3: Vectodmatrix form of gate-level degradation parameter for a or Based on this four-inputs NOR and NAND gates. 2.499 2.431 2.409 2.394 4. SIMULATION RESULTS 3'220 3.203 3'177 3.157 ~ Figure 2 shows a 4x4 bit multiplier circuit, whose simulation results will serve to verify The IDDM. The circuit has been de- 2.902 2.907 2.752 2.749 2.742 2.706 2.678 2.681 acterization process which consists of two tasks: 1. Obtain t vs. T curves (see eq. 1) using an electrical simu- lator like HSPICE. For each curve, a value of z and To is obtained by fitting the simulation data to (1 ). P 2. Task 1 is done repeatedly using different values of C ,  and z~~ . The resulting z and To data is fitted to ( 3 )  and a value of A. B and C obtained. The two phases are carried out for each glitch collision. Qual- itatively, the results obtained for all gates analyzed are quite similar in the sense that simulation data can be easily fitted to (1) and (3). validating the degradation model. Gates ranging from 1 to 4 inputs have been analyzed. As an example, we present the results for a NAND4 and a NOR4 gates in Table 3.  It can be easily observed in Table 3 how A, B and C are almost independent of the first changing input 0') in type-2 collisions. signed in a 0.6pm CMOS technology. In order to compare different types of simulation, we will ob- tain results using HSPICE and a logic simulator which imple- ments the IDDM and a conventional (without degradation) delay model (CDM). Figure 3 includes the simulation results of the input sequence Ox0,7x7,5xA, Ex6, FxF. It is observed that HSPICE and logic simulation with IDDM results are very similar, while simulation results from CDM shows much more output transitions than the others. This is due to the exclusion of degradation effect, making the glitches generated in the cir- cuit being propagated to the output. In both HSPICE and ID- DM, these glitches are degraded and, finally, rejected from the output. A very interesting aspect of the results are concerning the switching activity. Table 5 includes the measurement of the switching activity for logic simulation with IDDM and with V-485 AxB ’ O x 0  ’ 7x7 ’ SxA ’ Ex6 ’ FxF ’ I I I I /  i 7 Sequence OxO.7x7.5xA. Ex6. FxF Figure 2: 4x4 Multiplier circuit Events Filtered events DDhl I CDM IO\ern.CDhl DDM I CDAl  959 I 1411 I 47% 27 I 1 Table 5: . Logic simulation results statistics I I I I I OXO, FxF,OxO, FxF, ... I 1312 I 1992 1 52% I 66 I 6 CDM of two input patterns. It is very significative that the use of conventional delay models can produce an overestimation in switching activity up to the 40%. 5. CONCLUSIONS A way to extend the degradation delay model to the gate level has been presented. Those input collisions that may cause deg- radation effect (glitch collisions) have been analyzed and clas- sified. Two models are presented an exhaustive one which assigns a set of degradation parameters to each glitch collision, and a simplified one which associates a set of parameters to each input, instead to each collision. The simplifies model has similar accuracy but reduces both the number of parameters and the complexity of the characterization process.’This model allows to, obtain logic simulation results very similar to the HSPICE results and overcome conventional delay model defi- ciencies. 6. REFERENCES [ 11 L. Bisdounis, S. Nikolaidis, 0. Koufopavlou. “Analytical Tran- sient Response and Propagation Delay Evaluation of the CMOS Inverter for Short-Channel Devices”. IEEE J. of Solid-state Circ. pp. 302-306. Vol. 33, no. 2, Feb. 1998. [2] J.M. Daga. D. Auvergne. “A Comprehensive Delay Macro Mod- eling for Submicrometer CMOS Logics”. IEEE J. of Solid State Circuits. Vol. 34, No. 1, Jan. 1999. [3] A.I. Kayssi, K.A. Sakallah, T.N. Mudge. “The Impact of Signal Transition Time on Path Delay Computation”. IEEE Trans. on F , I 0 1 0  1 5  20 25 9 1 1 A X B  oxo x7 -;A 6 FxF * I I 1 I 1  17 I n  \ I I I \ I I I I \ 1 I I I I Y .  ! I .ss I I I I I \ I . , b). s2 \ I \  A I I I I I I I 0 5 1s 1 20 1 \ I  :15 !I 12 .- f SO 1 0  I I 1 I I 1 I 1 1 A x B  Ox0 . 7x7 SxA . E x G  I FxF , I ,ns, , \ 17 d I J 0 1 0  1 5  20 25 Figure 3: Simulation results of ide“‘dxO,7x7,5xA, Ex6, FxF multiplication sequence with a) HSPICE, b) IDDM. c) CDM Circuits and Systems-11: Analog and Digital Signal Processing, Vol. 40, No. 5, pp. 302-309, May 1993. Waveform Slope Effects in CMOS Delays”. IEEE J. of Solid- State Circ., Vol. 25, No. 6, pp. 1588-1590. Dec. 1990 [5] E. Melcher, W. Rothig, M. Dana. “Multiple Input Transitions in CMOS Gates”. Microprocessing and Microprogramming 35 (1992) pp. 683-690. North Holland. 161 S. H. Unger. “The essence of logic circuits”. Ed. Prentice-Hall International. Inc. 1989 [7] M.J. Bellido-Diaz, J. Juan-Chico. A.J. Acosta, M. Valencia, J.1,. Huertas. “Logical modelling of delay degradation effect in static CMOS gates”. IEE Proc. Circuits Devices and Systems, Vol. 147, [8] J. Juan-Chico, P. Ruiz-de-Clavijo, M.J. Bellido, A.J. .4costa, h4. Valencia. “Inertial and degradation delay model for CMOS logic gates”. In Proc. IEEE International Symposium on Circuits and Systems (ISCAS) 2000, pp. 1-459-461, Geneva, May 2000. [9] J. Juan-Chico, P. Ruiz-de-Clavijo, M.J. Bellido, A.J. Acosta, R4. Valencia: “Degradation delay model extension to CMOS gates”. In Proc. Power and Timing Modelling, Optimization and Simula- tion (PATMOS) 2000, pp. 149-158, Sept. 2000. [4] D. Auvergne, N. Azemard, D. Deschacht, M. Robert. “Input NO. 2 ,  pp. 107-1 17, April 2000. V-486 

Gate-Level Simulation of CMOS Circuits Using the IDDM Model

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Gate-Level Simulation of CMOS Circuits Using the IDDM Model

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