This letter reports a study on the effect of a hydrogen anneal after silicon pillar etch of surround-gate vertical MOSFETs intended for RF applications. A hydrogen anneal at 800 ?C is shown to give a 30% improvement in the drive current of 120-nm n-channel transistors compared with transistors without the hydrogen anneal. The value of drive current achieved is 250 ?A/?m, which is a record for thick pillar vertical MOSFETs. This improved performance is obtained even though a sacrificial oxidation was performed prior to the hydrogen anneal to smooth the pillar sidewall. The values of subthreshold slope and DIBL are 79 mV/decade and 45 mV/V, respectively, which are significantly better than most values reported in the literature for comparable devices. The H2 anneal is also shown to decrease the OFF-state leakage current by a factor of three

Abuelgasim, A.

Ashburn, P.

de Groot, C.H.

Hakim, M.M.A.

Hall, S.

Redman-White, W.

Tan, L.

English

M. M. A. Hakim

A. Abuelgasim

L. Tan

C. H. de Groot

W. Redman-White

S. Hall

P. Ashburn

Crossref

IEEE Electron Device Letters

Improved Drive Current in RF Vertical MOSFETS Using Hydrogen Anneal

Southampton (e-Prints Soton)

IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 3, MARCH 2011 279Improved Drive Current in RF Vertical MOSFETSUsing Hydrogen AnnealM. M. A. Hakim, A. Abuelgasim, L. Tan, C. H. de Groot, Senior Member, IEEE,W. Redman-White, Senior Member, IEEE,S .H a l l ,Senior Member, IEEE, and P. Ashburn, Member, IEEEAbstract—This letter reports a study on the effect of a hy-drogen anneal after silicon pillar etch of surround-gate verticalMOSFETs intended for RF applications. A hydrogen anneal at800 ◦C is shown to give a 30% improvement in the drive currentof 120-nm n-channel transistors compared with transistors with-out the hydrogen anneal. The value of drive current achieved is250 μA/μm, which is a record for thick pillar vertical MOSFETs.This improved performance is obtained even though a sacriﬁcialoxidation was performed prior to the hydrogen anneal to smooththe pillar sidewall. The values of subthreshold slope and DIBL are79 mV/decade and 45 mV/V, respectively, which are signiﬁcantlybetter than most values reported in the literature for comparabledevices. The H2 anneal is also shown to decrease the OFF-stateleakage current by a factor of three.Index Terms—Fillet local oxidation (FILOX), hydrogen anneal,vertical MOSFET.I. INTRODUCTIONSURROUND-GATE thick pillar vertical MOSFETs are be-ing researched because they offer a high drive currentper unit silicon area and can be easily integrated in a matureCMOS technology for low-cost RF transistors [1]–[5]. Oneof the challenges of vertical MOSFETs for this application issusceptibility to surface roughness and etch damage on thesidewalls of the silicon pillar. Sidewall roughness and etchdamage are caused by lithography and reactive ion etching(RIE) processes and give rise to mobility degradation due tosurface roughness scattering. Dry etch damage also occursduring polysilicon gate etch, and we have recently shown howthe device architecture and the Fillet local oxidation (FILOX)process can be optimized to eliminate damage during gate etch[6]. Pillar sidewall roughness is usually reduced by means ofsacriﬁcial oxidation, which has the effect of smoothing thesidewall surface. The surface morphology of silicon is alsoknown to be affected by hydrogen (H2) annealing and hasbeen investigated in the past for FinFET technology [7]. Atnanometer pillar dimensions, the smoothing of the ﬁn surfaceis easily achieved by H2 anneal, but in thick pillar verticalMOSFETs, it is not clear that the H2 anneal will have sucha signiﬁcant beneﬁcial effect. To date, there have been noManuscript received November 16, 2010; revised December 9, 2010;accepted December 9, 2010. Date of publication February 4, 2011; date ofcurrentversion February 23, 2011.This work was supported by the Engineeringand Physical Sciences Research Council, U.K. The review of this letter wasarranged by Editor J. Cai.M. M. A. Hakim, A. Abuelgasim, C. H. de Groot, W. Redman-White, andP. Ashburn are with the Nano Research Group, University of Southampton,SO17 1BJ Southampton, U.K. (e-mail: mmah@ecs.soton.ac.uk).L. Tan and S. Hall are with the Department of Electrical Engineering andElectronics, University of Liverpool, L69 3GJ Liverpool, U.K.Digital Object Identiﬁer 10.1109/LED.2010.2101042Fig. 1. Cross-sectional SEM image of the completed surround-gate verticalMOSFETs (a) without and (b) with H2 anneal.reports in the literature on the effects of such annealing on theperformance of vertical MOSFETs.In this letter, we, therefore, report, for the ﬁrst time, the effectof H2 annealing on the characteristics of vertical MOSFETswith large pillar dimensions. It is shown that H2 annealinggives a signiﬁcant improvement in drive current even aftera sacriﬁcial oxidation has been performed. H2 annealing of120-nm n-MOSFETs also has an excellent subthreshold slopeof 79 mV/decade and a DIBL of 45 mV/V.II. DEVICE FABRICATIONBoron-doped (0.75–1.25 Ω · cm) (100) wafers were taken asthe starting material, and a p-type body was formed by boronimplantation (2 × 1014 cm−2, 100 keV) and a thermal drive in.Then, oxide “hard mask” was formed, and RIE was used todeﬁne a 350-nm Si pillar. To eliminate the dry etch damageand to reduce the surface roughness on the pillar sidewall, a20-nm oxide layer was grown by dry oxidation at 900 ◦C andwas stripped off using an HF dip. The H2 anneal was performedfor 3 min in an ASM Epsilon II epitaxial reactor in 100% H2 ata pressure of 40 torr and a temperature of 800 ◦C. Then, a so-called Frame-gate FILOX vertical MOSFET was implementedin these Si pillars in a mature CMOS technology using 0.5-μmSCMOS design rules, full details of which are given in [6].III. RESULTSFig. 1 shows the cross-sectional SEM micrographs ofthe completed Frame-gate vertical MOSFET (a) without and0741-3106/$26.00 © 2011 IEEE280 IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 3, MARCH 2011Fig. 2. Comparison of output characteristics of 120-nm n-channel surround-gate vertical MOSFETs with and without a H2 anneal during the DOT mode ofoperation.Fig. 3. Transfer characteristics of 120-nm n-channel surround-gate verticalMOSFETs with and without H2 anneal during the DOT mode of operation.( b )w i t haH 2 anneal after stain etch. No signiﬁcant differencein the pillar height and width could be found for the deviceswith and without a H2 anneal. The devices exhibit identicalvalues of junction depth (190 nm) and channel length (120 nm).Similarly, high magniﬁcation images showed no discernabledifference in pillar shape after H2 anneal.Fig. 2 shows the output characteristics of 120-nm surround-gate vertical MOSFETs with and without H2 anneal duringthe drain-on-top (DOT) mode of operation. The H2 annealedtransistor shows a signiﬁcantly improved drive current in com-parison to the device without H2 anneal. The drive currents fora gate voltage overdrive of 1 V and a VDS of 1.5 V are found tobe250and190μA/μmfordeviceswithandwithoutH2 anneal,respectively, indicating a 30% drive current improvement. Mea-surements were performed on multiple transistors with a varietyof different channel widths, and a similar 30% improvement inperformance was observed at all widths. A similar trend wasalso observed for source-on-top (SOT) operation.Fig. 3 shows the transfer characteristics of 120-nm surround-gate vertical MOSFETs during the DOT mode of operation. Forthe device without H2 anneal, a subthreshold slope of 80 mV/decade and a DIBL of 40 mV/V are observed. For the H2 an-nealed device, a similar subthreshold characteristic is observedwith a subthreshold slope and DIBL of 79 mV/decade and45 mV/V, respectively. However, the H2 anneal appears to haveTABLE ICOMPARISON OF RESULTS OF THE 120-nm SURROUND-GATE VERTICALMOSFETs WITH AND WITHOUT H2 ANNEAL WITH REPORTED RESULTSFROM THE LITERATURE. Ion HAS BEEN CALCULATED FOR VDS = VDDAND FOR A 1-V GATE OVERDRIVE.T O ENSURE A MEANINGFULCOMPARISON,F ULLY DEPLETED THIN PILLAR VERTICALMOSFETs ARE EXCLUDED FROM THE TABLEreduced the threshold voltage (VT). While the device withoutH2 anneal exhibited a threshold voltage of 0.28 V, the thresholdvoltage of the H2 annealed device is found to be reduced to avalueof0.20V.H2 annealingalsoreducesthe OFF-stateleakagecurrent which is around a factor of three for a drain bias of50 mV. A similar effect of the H2 anneal is observed for SOTmode of operation.IV. DISCUSSIONTheaforementioned resultsshowthatthebeneﬁcial effects ofH2 anneal can be exploited on thick pillar vertical MOSFETssuitable for RF applications in a mature CMOS technology.Table I compares the electrical results of our vertical MOSFETswith other such devices reported in the literature. As can beseen, the H2 annealed device has a state-of-the art value of drivecurrent, as well as maintaining excellent values of subthresholdslope and DIBL. While the majority of the devices exhibits adrive current of ≤ 200 μA/μm at the bias conditions presentedin Table I, the H2 annealed device exhibits a drive current of250 μA/μm even though the device has a slightly longerchannel length of 120 nm. We have also compared the siliconarea of our fabricated vertical MOSFETs with comparablelateral MOSFETs using 0.5-μm design rules, and it is foundthat the vertical MOSFETs give a 53% area saving for a 36-μmchannel width. The peak transconductances (GM) of H2 an-nealed transistors were measured, and the values of 1.4 × 10−3and 1.1 × 10−2 A/V were obtained for VDS = 0.05 and 1 V,respectively, which are noticeably better than those reportedfor planar MOSFETs with comparable 0.5/0.7-μm technology[8], [9] and also better than some aggressively scaled planarMOSFETs reported in [9] and [10]. This beneﬁcial effect ofthe H2 anneal could be integrated with our recently reportedFILOX process for overlap capacitance reduction and silicida-tion process for S/D series resistance reduction [5] to deliver asigniﬁcant beneﬁt from VMOS devices for RF applications inmature lateral CMOS technologies.The improved drive current in the 120-nm H2 annealeddevice can be explained by surface smoothing due to the H2anneal and also by reduction of the interface state density (Dit)[7]. Hence, the mobility degradation associated with surfaceroughness scattering is reduced, thereby giving a drive currentimprovement.However,theH2 annealalsogivesaVT reductionHAKIM et al.: IMPROVED DRIVE CURRENT IN RF VERTICAL MOSFETS USING HYDROGEN ANNEAL 281Fig. 4. Measured pillar sidewall capacitance (CPL SIDEWALL) as a functionof voltage. Results are presented for capacitors with and without H2 anneal.of around 80 mV. Such a reduction of VT has also been reportedfor H2 annealed FinFETs in the past and has been explainedby the loss of ﬁn width and height due to the H2 anneal[7]. However, Fig. 1 shows that, for the thick pillar verticalMOSFETs of this letter, there is no noticeable loss of pillarheight and width due to the H2 anneal, and hence, VT reductionin these devices merits discussion.Fig. 4 shows CPLSIDEWALL measured at 1 MHz as afunction of gate voltage for pillars with and without H2 an-neal. These measurements were performed on sidewall testcapacitors, which were realized by dry etching of the gatepolysilicon. As can be seen, the accumulation capacitance inthe H2 annealed capacitor is signiﬁcantly higher than that in theunannealed capacitor. The gate oxide leakage currents in thetwo types of capacitors are identical, and hence, this impliesthat the gate oxide in the H2 annealed capacitor is thinner thanthat in capacitors without H2 anneal. This is understandable asa rough surface, and dangling bonds usually favor oxidation.Using the method described in [11], the estimated gate oxidethicknesses are found to be 2.6 and 2.8 nm for the deviceswith and without H2 anneal, respectively. A 0.20-nm reductionof oxide thickness accounts for approximately half (36 mV)of the observed 80-mV VT reduction and contributes to only8% of the observed drive current improvement. The rest of the44 mV of VT reduction can be explained by a reduction in theacceptor-type interface state density in the upper half of the Sibandgap, as can be seen from the slightly steeper slope andreduced CPLSIDEWALL in inversion for the hydrogen annealedcapacitor (inset in Fig. 4). Evidence of such a reduction inDit is also apparent from the reduced OFF-state leakage ofthe H2 annealed transistor (Fig. 3), as interface states areknown to enhance GIDL in MOSFETs [12]. The symmetry inthe observed GIDL and VT reductions during DOT and SOToperation of the H2 annealed transistors implies a similar Ditreduction at the pillar top and bottom. A lower Dit near the S/Dregions would reduce GIDL, while a reduced Dit in the channelwould affect VT. A rough estimation of the Dit reduction canbe obtained from the VT reduction in the H2 annealed transistorwhich is found to be 3.5 × 1011 cm−2. Theoretically, such areduction of Dit has a minor effect on the subthreshold slope(1.5 mV/decade).V. C ONCLUSIONHydrogen anneal at 800 ◦C has been applied after siliconpillar etch and sacriﬁcial oxidation to improve the surfaceroughness of thick pillar vertical MOSFETs suitable for RFapplications in a mature CMOS technology. It has been shownthat the hydrogen anneal gives a signiﬁcantly increased drivecurrent and a three times lower OFF-state leakage. For 120-nmchannel length transistors, the hydrogen anneal gives a 30%improvement in drive current in comparison to devices withoutthe hydrogen anneal. The values of drive current achievedconstitute the state of the art for thick pillar vertical MOSFETs.The transistors also have an excellent subthreshold slope of79 mV/decade and a DIBL of 45 mV/V. The electrical resultsshow that the hydrogen anneal has reduced the threshold volt-age by approximately 0.08 V. Capacitance/voltage measure-ments have shown that this can be explained by a combinationof a thinner gate oxide and a reduced acceptor-type interfacestate density on the hydrogen-smoothed pillar sidewall.REFERENCES[1] T. Schulz, W. Rösner, L. Risch, A. Korbel, and U. Langmann, “Short-channel vertical sidewall MOSFETs,” IEEE Trans. Electron Devices,vol. 48, no. 8, pp. 1783–1788, Aug. 2001.[2] E. Gili, C. H. Groot, V. D. Kunz, T. Uchino, P. Ashburn, D. C. Donaghy,S. Hall, Y. Wang, and P. L. F. Hemment, “Single, double & surroundgate vertical MOSFETs with reduced parasitic capacitance,” Solid StateElectron., vol. 48, no. 4, pp. 511–519, Apr. 2004.[3] J. M. Hergenrother, D. Monroe, F. P. Klemens, A. Komblit, G. R. Weber,W. M. Mansﬁeld, M. R. Baker, F. H. Baumann, K. J. Bolan, J. E. Bower,N. A Ciampa, R. A. Cirelli, J. I. Colonell, D. J. Eaglesham, J. Frackoviak,H. J. Gossmann, M. L. Green, S. J. Hillenius, C. A. King, R. N. Kleiman,W. Y. C. Lai, J. T.-C. Lee, R. C. Liu, H. L. Maynard, M. D. Morris,S.-H. Oh, C.-S. Pai, C. S. Rafferty, J. M. Rosamilia, T. W. Sorsch, andH.-H. Vuong, “The vertical replacement (VRG) MOSFET: A 50 nmvertical MOSFET with lithography-independent gate length,” in IEDMTech. Dig., 1999, pp. 75–78.[4] K. Mori, A. Duong, and W. F. Richardson, “Sub-100 nm verticalMOSFET with threshold voltage adjustment,” IEEE Trans. Electron De-vices, vol. 49, no. 1, pp. 61–66, Jan. 2002.[5] M. M. A. Hakim, L. Tan, A. Abuelgasim, K. Mallik, S. Connor,A. Bousquet, C. H. de Groot, W. Redman-White, S. Hall, and P. Ashburn,“Self-aligned silicidation of surround gate vertical MOSFETs for low costRFapplications,”IEEETrans.ElectronDevices,vol.57,no.12,pp.3318–3326, Dec. 2010.[6] M. M. A. Hakim, L. Tan, O. Buiu, W. R. White, S. Hall, and P. Ashburn,“Improved sub-threshold slope in short channel vertical MOSFETS usinga FILOX oxidation,” Solid State Electron., vol. 53, no. 7, pp. 753–759,Jul. 2009.[7] W. Xiong, G. Gebara, J. Zaman, M. Gostkowski, B. Nguyen, G. Smith,D. Lewis, C. R. Cleavelin, R. Wise, S. Yu, M. Pas, T.-J. King, andJ.P.Colinge,“ImprovementofFinFETelectrical characteristics byhydro-gen annealing,” IEEE Electron Device Lett., vol. 25, no. 8, pp. 541–543,Aug. 2004.[8] J.-C. Gou, M.-C. Chang, C.-Y. Lu, C. C.-H. Hsu, andS. S.-S. Chung, “Transconductance improvement due to back biasfor submicron NMOSFET,” IEEE Trans. Electron Devices, vol. 42, no. 2,pp. 288–294, Feb. 1995.[9] G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, S. Rishton, and E. Ganin,“High transconductance and velocity overshoot in NMOS devices at the0.1- μm gate-length level,” IEEE Electron Device Lett., vol. 9, no. 9,pp. 464–466, Sep. 1988.[10] A. Cester, S. Gerardin, A. Tazzoli, and G. Meneghesso, “Electrostaticdischarge effects in ultrathin gate oxide MOSFETs,” IEEE Trans. DeviceMater. Rel., vol. 6, no. 1, pp. 87–94, Mar. 2006.[11] B. Ricco, P. Olivo, T. N. Nguyen, T.-S. Kuan, and G. Ferriani, “Oxidethickness determination in thin-insulator MOS structures,” IEEE Trans.Electron Devices, vol. 35, no. 4, pp. 432–438, Apr. 1988.[12] I.-C. Chen, C. W. Teng, D. J. Coleman, and A. Nishimura, “Interface-trap enhanced gate-induced leakage current in MOSFET,” IEEE ElectronDevice Lett., vol. 10, no. 5, pp. 216–218, May 1989.

and J.P.Colinge,“ImprovementofFinFETelectrical characteristics byhydrogen annealing,”

Electrostatic discharge effects in ultrathin gate oxide MOSFETs,”

High transconductance and velocity overshoot in NMOS devices at the 0.1- μm gate-length level,”

Improved sub-threshold slope in short channel vertical MOSFETS using a FILOX oxidation,”

Interfacetrap enhanced gate-induced leakage current in

Oxide thickness determination in thin-insulator

Self-aligned silicidation of surround gate vertical MOSFETs for low cost RFapplications,”IEEETrans.ElectronDevices,vol.57,no.12,pp.3318– 3326,

Shortchannel vertical sidewall MOSFETs,”

Single, double & surround gate vertical MOSFETs with reduced parasitic capacitance,”

Sub-100 nm vertical MOSFET with threshold voltage adjustment,”

The vertical replacement (VRG) MOSFET: A 50 nm vertical MOSFET with lithography-independent gate length,”

Transconductance improvement due to back bias for submicron NMOSFET,”

Improved drive current in RF vertical MOSFETS using hydrogen anneal

https://eprints.soton.ac.uk/272059/1/05706339.pdf

Improved drive current in RF vertical MOSFETS using hydrogen anneal

Abstract

Similar works

Full text

Available Versions

Crossref

Southampton (e-Prints Soton)