Modern power electronics devices require grid synchronization to accurately time the switching of their semiconductor devices. This project steps through the development of such an algorithm for three-phase grids. The classical synchronous reference frame phase-locked loop is studied in depth, including a detailed analysis of the transforms that give rise to its name. A few improvements are added in order to mitigate some of the well-known pitfalls of this method. Using the theory of symmetrical sequence components, new equations that describe the behaviour of said components in relation to unbalanced three-phase voltages are derived. These equations are then used to better understand the behaviour of the classical algorithm under unbalanced conditions. From this, an advanced grid synchronization algorithm based on multiple phase-locked loops is developed. This algorithm is then discretized and implemented in a typical microcontroller. Finally, a custom genetic algorithm is used to fine-tune the parameters of the algorithm to a specific simulated scenario meant to represent harsh grid conditions
