Ahmed, H.

Amakawa, S.

Durrani, Z. A. K.

Furuta, Y.

Kamiya, T.

Mizuta, Hiroshi

Nakazato, K.

Tan, Y. T

English

Tan, Y. T.

Ahmed, H,

Southampton (e-Prints Soton)

 1 mizuta@phy.cam.ac.uk NANOSILICON FOR SINGLE-ELECTRON DEVICES    H. Mizuta1,4, Y. Furuta1,4, T. Kamiya2,4, Y. T. Tan3,4, Z.A.K. Durrani3,4, K. Nakazato1,4 and H. Ahmed3,4  1Hitachi Cambridge Laboratory, Hitachi Europe Ltd., Madingley Road, Cambridge CB3 0HE UK 2Materials and Structures Laboratory, Tokyo Institute of Technology, 4259 Nagatsuka,  Midori-ku, Yokohama 226-8503, Japan 3Microelectronics Research Centre, University of Cambridge, Madingley Road, Cambridge CB3 0HE, UK 4CREST JST (Japan Science and Technology), Shibuya TK Bldg., 3-13-11 Shibuya, Tokyo 150-0002, Japan   This paper gives an overview of our recent work investigating nano/polycrystalline silicon nanostructures for single-electron device applications.  Nano/poly-Si nanowires have been used as a key building block for nanoscale memory and logic devices based on the Coulomb blockade phenomenon by utilising individual silicon grains and grain boundaries as an electron island and a tunnel junction. However, the microscopic properties of the grain boundaries as a tunnel barrier have not been made clear, and there is no guideline to optimise the grains and grain boundaries in terms of high temperature Coulomb blockade operation.   We first provide a short summary on the research of silicon-based single-electron devices from the last decade. Various single-electron transistor structures are compared in terms of control of electron islands and tunnel barriers. We then investigate the single-electron charging phenomena in nano/polycrystalline silicon nanostructures. A novel point-contact transistor (Fig. 1) is introduced, which features an extremely short and narrow nano/poly-Si nanowire as the transistor’s channel [1]. This structure is suitable for studying how a grain smaller than 10 nm in size and a discrete grain boundary work as a charging island and a tunnel barrier, respectively. The relationships between structural and electrical parameters of grains/grain-boundaries and the resulting Coulomb blockade characteristics (Fig. 2) [2] for the point contact transistors are investigated by applying various passivation processes such as multiple step oxidation [3][4]. Finally, a possibility of controlling and optimising grain and grain-boundary properties is discussed for improving the Coulomb blockade characteristics and realizing nano/poly-Si single-electron transistors operating at room temperature [5].  [1] Y. Furuta, H. Mizuta, K. Nakazato, Y. T. Tan, T. Kamiya, Z. A. K. Durrani, H. Ahmed and K. Taniguchi, Jpn. J. Appl. Phys. 40, L615 (2001). [2] Y. Furuta, H. Mizuta, K. Nakazato, T. Kamiy.a, Y. T. Tan, Z. A. K. Durrani and K. Taniguchi, Jpn. J. Appl. Phys. 41, 2675 (2002) [3] T. Kamiya, Z.A.K. Durrani and H. Ahmed, Appl. Phys. Lett. 81, 2388 (2002) [4] T. Kamiya, Y.-T. Tan, Z.A.K. Durrani and H. Ahmed: J. Non-Cryst. Solids 299-302, 405 (2002). [5] Z.A.K. Durrani, T. Kamiya, Y.T. Tan, H. Ahmed and N. Lloyd, Microelectronic Engineering 63, 267 (2002) 2     Fig. 1 A SEM image of an as-prepared point contact transistor with a channel 30-nm-wide and 30-nm-long. The inset figure shows the grain structure of Secco-etched poly-Si film. Lateral dimension of grains in the film ranges from 20 nm to 150 nm.  Fig. 2 Two types of Ids-Vgs characteristics observed for point-contact transistors oxidized at 1000 o C for 15 minutes. Difference in the Coulomb oscillation period and current peak-to-valley ratio are attributed to different size of charging island and tunnel barrier properties.   -10 0 10-15-10-50-1 0 1-3.05-3-2.95-2.9(a) (b)Vgs (V) Vgs (V)Ids(nA)Ids(nA)-2 mVVds=-2 mV-6 mVVds=-10 mV-10 0 10-15-10-50-1 0 1-3.05-3-2.95-2.9(a) (b)Vgs (V) Vgs (V)Ids(nA)Ids(nA)-2 mVVds=-2 mV-6 mVVds=-10 mV 

Nanosilicon for single-electron devices

Nanosilicon for single-electron devicesH. Mizutaa,b,*, Y. Furutaa,b,1, T. Kamiyab,c, Y.T. Tanb,d,2, Z.A.K. Durranib,d,S. Amakawad, K. Nakazatoa,b, H. Ahmedb,da Hitachi Cambridge Laboratory, Hitachi Europe Ltd., Cavendish Laboratory, Madingley Road, Cambridge CB3 0HE, UKb CREST JST (Japan Science and Technology), Shibuya TKBldg., 3-13-11 Shibuya, Tokyo 150-0002, Japanc Materials and Structures Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503, Japand Microelectronics Research Centre, University of Cambridge, Madingley Road, Cambridge CB3 0HE, UKAbstractThis paper presents a brief overview of the physics of nanosilicon materials for single-electron device applications. We study howa nanosilicon grain and a discrete grain boundary work as a charging island and a tunnel barrier by using a point-contact transistor,which features an extremely short and narrow channel. Single-electron charging phenomena are investigated by comparing as-prepared devices and various oxidized devices. The optimization of grain and grain-boundary structural parameters is discussed forimproving the Coulomb blockade characteristics and realizing room temperature device operation.  2003 Published by Elsevier B.V.PACS: 81.07.Bc; 73.23.Hk; 85.35.GvKeywords: Nanocrystalline silicon; Single-electron device; Coulomb blockade1. Introduction––why nanosilicon?The progress of nanofabrication technologies overthe last two decades as allowed us to explore a new re-search ﬁeld of single electronics [1]. Single-electroncharging or Coulomb blockade (CB)’ phenomena areexpected to appear in semiconductor nanostructures andhave been adopted as a new principle for manipulating asmall number of electrons. Both for memory and logicapplications, single-electron devices (SEDs) have beenstudied intensively to overcome the inherent scalabilityissue of the conventional CMOS devices. A key buildingblock for SEDs is the multiple tunnel junction (MTJ),which is composed of multiple tunnel barriers andelectron islands. As a general guideline, the MTJ shouldmeet the following two requirements to show the CBeﬀects at a temperature T:Rt   RQ ¼ h=e2 ¼ 25:6k X; ð1ÞEC ¼ e2=2CR   kBT ð2Þto avoid quantum and thermal smearing of the elec-tronic states conﬁned in the electron islands. In Eqs.(1) and (2) RQ is the quantum resistance, Rt is thezero-bias tunnel resistance of the (generally nonlinear)current-voltage characteristic of a tunnel junction, ECis the charging energy, and CR is an island capaci-tance.A number of fabrication methods of MTJs have beenreported based on crystalline silicon. These structuresmay be classiﬁed into two groups in terms of the mannerof deﬁning electron islands: patterned electron islandsand naturally formed ones. A patterned electron islandwith a lateral size of less than 10 nm has been real-ized by using a pattern-dependent oxidation (PADOX)technique [2]. This technique utilizes an increase in aband gap due to quantum conﬁnement in an ultra-narrow channel and a decrease in a band gap due tocompressive stress in the channel after oxidation process*Corresponding author. Present address: Department of PhysicalElectronics, Tokyo Institute of Technology, 2-12-1 Okayama, Meguro-ku, Tokyo 152-8552, Japan. Tel./fax: +81-3-5734-3591.E-mail address: mizuta@pe.titech.ac.jp (H. Mizuta).1 Present address: Electronics, Information Systems and EnergyEngineering, Osaka University, 2-1 Yamada-oka, Suita, Osaka 565-0871, Japan.2 Present address: Institute of Microelectronics, 11 Science ParkRoad, Science Park 2, Singapore 117685, Singapore.1567-1739/$ - see front matter   2003 Published by Elsevier B.V.doi:10.1016/j.cap.2003.10.005Current Applied Physics 4 (2004) 98–101www.elsevier.com/locate/cap[3]. Naturally formed structures exploit various kinds oflocal disorder in patterned nanoscale structures. In aheavily doped Si wire [4] a few tens of nanometers inwidth, randomly distributed dopant atoms cause po-tential ﬂuctuations, and a linear chain of electron islandscan form naturally [5]. Because of its simplicity this MTJstructure has often been used for making CB memoryand logic devices. However, the CB oscillation canusually be observed only at temperatures below 77 K asthe tunnel barriers are not high enough to conﬁneelectrons at high temperatures. A surface roughness in-duced MTJ has also been reported for a very narrowMOS channel [6], and the CB oscillation was observedat room temperature for this structure. Among thesemethods, PADOX is the most favorable as the size andposition of an electron island can be controlled. How-ever, key parameters of tunnel barriers such as thebarrier height and thickness are not controllable withthis method.Compared with these methods, nanosilicon is anattractive bottom-up approach for forming ultra-smallcharging islands, and several fabrication techniqueshave been developed. The ﬁrst method is to use a verythin poly/nanocrystalline (nc) silicon ﬁlm with the sizeof the grains down to a few nanometer. The poly/nc-Siﬁlms can be formed either from an amorphous Si ﬁlmwith solid phase crystallization (SPC) or by using avery high frequency (VHF) plasma-enhanced chemicalvapour deposition (PECVD) at a low temperature [7].In the SPC ﬁlms the individual grains are usuallycolumnar shaped, and the grain boundaries (GBs)between adjacent grains contain carrier trap states dueto dangling bonds. On the other hand, in the PECVDﬁlms, the individual grains are more spherical, and theGBs are formed by a-Si:H layers between grains.Another approach is to use porous Si [8] formed byusing photoanodization of the Si substrate. The sur-face of the nc-Si islands formed in the substrate can beoxidised selectively by electrochemical oxidation. For-mation of a linear chain of nc-Si islands with adiameter as small as 5 nm has been observed [9]. Amore recent approach is an aerosol deposition tech-nique, VHF plasma enhanced deposition of silane witha hydrogen gas pulse sequence [10]. This techniquefacilitates in separating the nucleation and crystalgrowth process and helps to fabricate nc-Si particleswith diameter less than 10 nm and dispersions of 1 nm[11]. Particle diameter down to 3 nm has also beenreported recently [12]. The interparticle tunnel barrierscan be formed by in situ oxidation or nitridation in acontrolled manner.In this paper we focus on the ﬁrst approach based onpoly/nc-Si ﬁlms. We investigate structural and electricalproperties of nanosilicon grains and GBs and discussoptimisation of their parameters for room temperatureSED operation.2. Single-electron charging phenomenon in nanosiliconThe macroscopic properties of the poly-Si ﬁlm withlarge Si grains have been studied extensively for thedevelopment of thin ﬁlm transistors and static randomaccess memories, and various process techniques havebeen established to increase the grain size and to improvecarrier mobility. However, the microscopic properties ofindividual nanoscale grains and discrete GBs have notbeen studied in detail. In this work, we adopt a point-contact transistor (PC-Tr) [13], which has a channel withboth the length L and width W as small as the grain sizeLgrain of the nano/poly-Si ﬁlm. The electric characteristicsfor the PC-Trs must therefore reﬂect the properties ofindividual grains and GBs contained in the channel. Fig.1 shows an SEM image of a PC-Tr fabricated in a 50-nmthick SPC poly-Si ﬁlm. The inset (a) to Fig. 1 is a SEMimage of a Secco-etched poly-Si ﬁlm that shows theindividual grains and GBs. From the SEM observation itwas found that Lgrain in this particular ﬁlm ranges from20 to 150 nm. PC-Trs with W and L from 20 to 50 nmwere patterned by high-resolution e-beam lithographyandelectrically isolated by reactive ion etching. Electricalcharacterization was performed for both as-preparedPC-Trs and those oxidized at 1000  C for 15 min in dryO2 ambient. An eﬀective potential barrier height qVB ofGBs was extracted from a temperature dependence of theIds–Vds characteristics at between 200 and 300 K using thethermionic emission model.The as-prepared PC-Trs [13] did not show any Cou-lomb oscillation at temperatures above 4.2K. Fromthe TEM observation of grain structures, the tunnelcapacitance Ctunnel between two adjacent grains wasestimated to be larger than 80 aF. In addition, the tunnelresistance Rt was evaluated to be similar to RQ. There-fore both EC and Rt are not suﬃciently large to observethe CB eﬀect even at cryogenic temperatures. The bar-rier height qVB extracted for the as-prepared PC-Trs,ranges from 30 to 80 meV.In contrast, most of the oxidized PC-Trs show a clearCoulomb oscillation in the Ids–Vgs curves and a CoulombFig. 1. SEM image of an as-prepared PC-Tr. The insets (a) and (b)show the grain structure of the poly-Si ﬁlm and a blow-up of thechannel region, respectively.H. Mizuta et al. / Current Applied Physics 4 (2004) 98–101 99gap VT in the Ids–Vds characteristics associated with theCB eﬀect [14]: Fig. 2(a) and (b) show the Ids–Vds andIds–Vgs characteristics for one of the oxidized PC-Trs. Inthe oxidized PC-Trs, the poly-Si ﬁlm thickness decreaseddown to approximately18 nm after the oxidation process[16]. This leads to a decrease in Ctunnel and consequentlyincreases EC Although an increase in the mean qVB wasjust 5 meV for the oxidised PC-Trs, Rt was found to beby more than two orders of magnitude larger after theoxidation treatment because the GBs were oxidizedeﬀectively [17] and converted to suboxide. Both the in-creased EC and Rt result in the appearance of the CBeﬀect. The GB tunnel barrier thickness d was estimatedto be approximately 3 nm for the oxidized PC-Tr using atunneling current calculation and observed value of Rt.This is consistent with high-resolution TEM observa-tion, which reveals that GBs were oxidized faster thancrystalline grains and that some silicon suboxide layerswere as thick as 2–3 nm. The lateral dimensions of thegrain that acts as the charging island were evaluated tobe about 3 nm·10 nm by using a two-dimensionalcapacitance calculation and the observed VT and Cou-lomb oscillation period DVgs.3. Material optimisation towards room-temperature nano-silicon single-electron devicesIt was found from all the oxidized samples thatboth the P/V ratio and VT increase with Rt and that agood P/V ratio is observed when the total zero-biastunnel resistance of the device is over 1 MX [14]. If weassume Lgrain   3 nm and d   1 nm, a simple calculation[15] shows that qVB should meet the following condition:qVB   260 meVð 10kBTÞ: ð3ÞRegarding the grain size, it is apparent that decreas-ing Lgrain further is needed to reduce CR. For this pur-pose a nc-Si ﬁlm prepared by a low-temperature VHFPECVD [7] was adopted instead of the SPC poly-Si ﬁlm.A 20 nm thick nc-Si:H ﬁlm was prepared from aSiF4:H2:SiH4 gas mixture at temperatures 6300  C.From TEM observation it was found that the ﬁlmcontains grains with Lgrain from 4 to 8 nm uniformlydistributed in a-Si:H matrix (Fig. 3(a)).After deﬁning the PC-Trs in the same manner, amultiple step oxidation process was applied, which wasproposed to oxidize the a-Si:H selectively and to convertit to SiOx (x < 2) without increasing Lgrain [17,18]. This islow-temperature oxidation (650–750  C) followed byhigh-temperature (1000  C) annealing. A cross-sectionalTEM showed that the grains remained the same in sizedespite the fact that the overall ﬁlm thickness was re-duced by 6 nm due to surface oxide formation. qVB ex-tracted for the multi-step oxidised nc-Si PC-Tr withL ¼ W ¼ 20 nm was as high as 173 meV while that forthe as-deposited nc-Si PC-Trs was only about 40 meV.A clear CB oscillation was observed for the multi-stepoxidised nc-Si PC-Trs: the Ids–Vgs characteristics ob-served for the device with L ¼ W ¼ 20 nm is shown inFig. 3(b) [19]. The oscillation with an unchanged periodpersists up to room temperature although the P/V cur-rent ratio is gradually decreased as the temperatureFig. 2. (a) Ids–Vds and (b) Ids–Vgs characteristics for an oxidised PC-Trmeasured at T ¼ 5 K. Each Ids–Vds curve in (a) is oﬀset by 5 nA/100mV in Vgs.Fig. 3. (a) TEM image of the as-deposited PECVD nc-Si ﬁlm with ablow-up of a nano-Si grain in the inset and (b) Ids–Vgs characteristicsfor the multi-step oxidised nc-Si PC-Tr. The temperature increasesfrom 50 to 275 K in 25 K steps.100 H. Mizuta et al. / Current Applied Physics 4 (2004) 98–101increases as shown in the inset to Fig. 4, and that forroom temperature is still far too small for any kinds ofdevice application. From a simple capacitance calcula-tion combined with the observed DVgs and VT, Lgrain wasestimated to be about 8 nm for this nc-Si PC-Tr, whichis in good agreement with the TEM observation.Even further reduction of Lgrain is needed for realisingroom temperature SED operation. To provide a morequantitative guideline, the charging energy EC andquantum conﬁnement energy EK were calculated as afunction of nc-Si dot diameter. EC was calculated fora Si sphere embedded in oxide taking account of bothself-capacitance and tunnel capacitance [20]. EK wasobtained numerically as the energy of the lowest quasi-bound state of an intrinsic Si quantum well with 2-nm-thick oxide barriers: tunnel barrier heights of 3.0 and0.26 eV (Eq. (3)) were used for SiO2 and SiOx barriers.Fig. 4 shows the dot diameter dependence of EC (a lightgrey solid line), EK calculated for both SiO2 and SiOx(dotted lines) barriers and the corresponding total elec-tron addition energies ER (black and dark grey solidlines). Because of the ﬁnite tunnel barrier heights, EKapproaches its maximum with decreasing dot diameter.A region of a diameter ranging from 4 to 8 nm, whichcorresponds to the nc-Si ﬁlm used above, is indicated asa shaded region. Two horizontal broken lines show theenergy of 10kBT with T ¼ 300 K and T ¼ 77 K. Theseresults indicate thatLgrain   2nm ð4Þis needed to meet ER   10kBT at room temperature, and tosecure SED operation at room temperature, a furtherdevelopment is still needed towards 1-nm-scale size con-trol of nanosilicon dots. However, in this region, thesingle-electron charging phenomenon in the nanosiliconmaterial can certainly be a way of modulating currentsubstantially at room temperature, and it is then impor-tant to develop new device structures that can operatebased on the single-electron charging phenomenoncombined with other mechanisms of controlling ﬂow ofelectrons, such as the external electrostatic potential,tailored energy potential barriers [21], and energy quan-tization.4. SummaryNanosilicon has been investigated as a promisingmaterial for SEDs. We have shown that control ofmicroscopic properties of GBs as a tunnel barrier isessential to improve CB characteristics by comparing as-prepared and oxidised PC-Trs fabricated using the SPCpoly-Si ﬁlm and the PECVD nc-Si ﬁlm. We have foundthat qVB should be as large as 10kBT, and Lgrain shoulddecrease down to less than 2nm for any practical deviceapplications at room temperature.References[1] H. Grabert, M.H. Devoret (Eds.), Single Charge Tunneling––Coulomb Blockade Phenomena in Nanostructures, NATO ASISeries B, Plenum, New York, 1991.[2] Y. Takahashi, H. Namatsu, K. Iwadate, M. Nagase, K. Murase,IEEE Trans. Electron. Dev. 43 (1996) 1213.[3] S. Horiguchi, M. Nagase, K. Shirakashi, H. Kageshima, Y.Takahashi, K. Murase, Jpn. J. Appl. Phys. 40 (2001) L29.[4] R. Smith, H. Ahmed, J. Appl. Phys. 81 (1997) 2699.[5] G. Evans, H. Mizuta, H. Ahmed, Jpn. J. Appl. Phys. 40 (2001)5837.[6] H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, T. Hiramoto,T. Ikoma, Appl. Phys. Lett. 68 (1996) 3585.[7] T. Kamiya, K. Nakahata, Y.T. Tan, Z.A.K. Durrani, I. Shimizu,J. Appl. Phys. 89 (2001) 6265.[8] N. Koshida, H. Koyama, Appl. Phys. Lett. 60 (1992) 347.[9] A.G. Cullis, L.T. Canham, P.D.J. Calcott, J. Appl. Phys. 82(1997) 909.[10] S. Oda, M. Otabe, Mater. Res. Soc. Proc. 358 (1995) 721.[11] T. Ifuku, M. Otabe, A. Itoh, S. Oda, Jpn. J. Appl. Phys. 36 (1997)4031.[12] J. De Blauwe et al., IEDM Tech. Dig. (2000) 683.[13] Y. Furuta, H. Mizuta, K. Nakazato, Y.T. Tan, T. Kamiya,Z.A.K. Durrani, H. Ahmed, K. Taniguchi, Jpn. J. Appl. Phys. 40(2001) L615.[14] Y. Furuta, H. Mizuta, K. Nakazato, T. Kamiya, Y.T. Tan,Z.A.K. Durrani, K. Taniguchi, Jpn. J. Appl. Phys. 41 (2002) 2675.[15] T. Kamiya, Y. Furuta, Y.-T. Tan, Z.A.K. Durrani, H. Mizuta, H.Ahmed, in: Polycrystalline Semiconductors VII––Bulk Materials,Thin Films, and Devices, T. Sameshima, T. Fukui, H.P. Strunk,J.H. Werner (Eds.), Series Solid State Phenomena’, Scitech Publ.,Uettikon am See, Switzerland, 2003, pp. 351–354.[16] Y.T. Tan, Z.A.K. Durrani, H. Ahmed, J. Appl. Phys. 89 (2001)1262.[17] T. Kamiya, Z.A.K. Durrani, H. Ahmed, Appl. Phys. Lett. 81(2002) 2388.[18] T. Kamiya, Y.-T. Tan, Z.A.K. Durrani, H. Ahmed, J. Non-Cryst.Solids 299–302 (2002) 405.[19] Z.A.K. Durrani, T. Kamiya, Y.T. Tan, H. Ahmed, N. Lloyd,Microelectron. Eng. 63 (2002) 267.[20] K.K. Likharev, Proc. IEEE 87 (1999) 606.[21] K.K. Likharev, Appl. Phys. Lett. 73 (1998) 2137.Fig. 4. Dot diameter dependence of the charging energy EC thequantum conﬁnement energy EK, and the total electron addition en-ergy ER calculated for a Si sphere embedded in SiO2 or SiOx. An ellipseindicates ER corresponding to the nc-Si material used in the presentexperiment.H. Mizuta et al. / Current Applied Physics 4 (2004) 98–101 101

Devoret (Eds.), Single Charge Tunneling–– Coulomb Blockade Phenomena in Nanostructures,

in: Polycrystalline Semiconductors VII––Bulk Materials, Thin Films, and Devices,

Nanosilicon for single-electron devices

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