Ahmed, H.

Itoh, K.

Mizuta, Hiroshi

Nakazato, K.

English

Southampton (e-Prints Soton)

Ids,  $bo  channel material was grown at 400°C as a digital alloy superlattice with 10 periods of 4 ML InAs/l ML InSb [2]. Modu- lation doping was  achieved  through the use  of  a  thin Si-doped InAs layer located  125A above the channel [3]. The sheet carrier density and mobility of the starting material at 300K were  1.4 x 1012cm-2  and 13,400m2/Vs,  respectively. The HEMTs were fabri- cated using Pd/WAu source and drain ohmic contacts which were formed by heat treatment on a hot plate. A Cr/Au Schottky-gate was  then  formed using PMMA e-beam lithography and lift-off techniques. Finally, device isolation was achieved by wet chemical etching.  With  this  etch,  a  gate  air  bridge  was  formed  which extends from the channel to the gate bonding pad. To confii  the type I alignment between AlSb and InAs,,Sbo2, we  camed out photoluminescence (PL) measurements at 5K with a  Fourier  transform  infra-red  spectrometer.  Samples  were mounted on a cryogenic dewar and excited with an 810nm laser diode. The room-temperature blackbody radiation was eliminated by  a double-modulation technique [4]. Fig. 2 shows the PL spec- trum from the Idq,,Sbo2  single quantum well. In contrast to the nonluminous AlSb/lnAs single quantum wells, this sample exhibits bright luminescence at 272meV. The arrow in Fig. 2 indicates the measured bandgap energy for a thick InA~,Sb,, digital superlat- tice. Our results imply that the lowest sub-band energy for a l50A InAs,,Sbo2 quantum well  is 62meV, consistent with kp  calcula- v,,=ov, / 0 0  0.2  0.4  0.6  0.8 drain voltage, V  m Fig. 3 HEMT drain characteristics L, = O.lpn, L,,  = 1.2~,  W, = loop,  Vcs = O.lV/step gate voltage, V  m Fig. 4 HEMT transconductance and drain current against gate voltage VDs  = 0.6V The drain characteristics obtained for an HEMT with a 0.1~ gate length are shown in Fig. 3. The low-field source-drain resist- ance at V,,  = OV  is  1.2Q mm. The dependence of the transcon- ductance and drain current on the gate voltage at  V,,  = O.6V  is shown in Fig. 4. A maximum transconductance of  800mS/mm is observed at  V,, = -0.3V. The S-parameters of the HEMTs were measured  on-wafer from  1 to 40GHz. Based on the usual 6dB/ octave extrapolation, anfT of 130GHz and anfmax  of 80GHz were obtained at  VDs  = 0.6V and  V,,  = -0.4V.  Using  a  simplified equivalent  circuit,  the  microwave transconductance and  output conductance for a 1OOpn gate width device are 700 and llOmS/ mm, respectively, corresponding to a voltage gain of 6 at this bias condition. After subtraction of the gate bonding pad capacitance, an fr  of  18OGHz  is  obtained. The  highest ,La, observed  was 12OGHz which was measured on a device with ii  50pn  gate width that had an output conductance of SOmS/mm and a voltage gain of 9. The output conductance and voltage gain are the best values reported for a 0.1 pn antimonide-based HEMT. The improvement is believed to be caused by the confinement of holes in the channel as a result  of  the type  I  band lineup and the  lower A-L  valley energy separation which results in  more saturation of  the drain current. Improved high-speed performance should be possible with the  addition of  subchannel  designs  [3]  which  enable  improved charge control and reduced impact ionisation. Acknowledgment: This work was supported by the Office of Naval Research. The authors thank H.B. Dietrich, W.J. Moore, and B.V. Shanabrook for helpful discussions. 0 IEE 1999 Electronics Letters Online No: 19990536 DOI: 10.1049/el:19990536 J.B. Boos,  M.J. Yang,  B.R. Bennett,  D. Park,  W. Kruppa  and R. Bass  (Naval  Research  Laboratory,  Washington,  DC  20375-5320, USA) E-mail: boos@estd.nrl.navy.mil 3 March 1999 References 1  BOOS, J.B.,  KRUPPA, W.,  BENNETT, B.R.,  PARK, D..  KIRCHOEFER, S.W., BASS, R., and  DIETRICH, H.B.:  ‘AISb/InAs HEMT’s  for low-voltage, high-speed applications’, ZEEE  Trans., 1998, EI1-45,  (9), pp.  1869- 1875 2  BENNETT, B.R.,  SHANABROOK, B.v.,  and  TWIGG,  M.E.:  ‘Anion control in molecular  beam  epitaxy of mixed As/Sb 111-V heterostructures’, J. Appl. PhyS., 1999, 85, (4), pp. 2157-2161 3  BOOS, J.B.,  YANG, M.J.,  BENNETT, B.R.,  PARK, D.,  KNIPPA, W., YANG, c.H.,  and  BASS, R.:  ‘0.1 p AISb/InAs  HEMTs  with  InAs subchannel’, Electron. Lett., 1998, 34, (15), pp.  1525-1526 4  ROWELL, N.L.:  ‘Infrared  photoluminescence  of  intrinsic  InSb’, Infrared Phys., 1988, 28, (I), pp. 3742 Silicon stacked tunnel transistor for high- speed and high-density random access memory gain cells K. Nakazato, K. Itoh, H. Mizuta and H. Ahmed Novel stacked tunnel transistors have been  fabricated on silicon dioxide  using  a  standard  0.2~  silicon  process.  From  the measured characteristics it is shown that random access memory operations with  Ions read/write times are possible in cells which occupy the area of just one transistor. Introduction: Dynamic random  access  memories  (DRAMS) are used  as the main memories in computers because of their high- capacity and high-speed. Since there is no gain in present DRAM cells, they require large cell-capacitors to produce sufficiently large sense signals. The structure and fabrication processes have become increasingly complicated so as to maintain the large capacitance while further miniaturising  the cell in each new generation. In  this  Letter we  describe a  novel  stacked tunnel  transistor which enables a new gain cell to be realised for high-density and high-speed  random  access memories [l].  Since this  memory  cell has gain, a large capacitor is not necessary. The memory cell  is vertically structured, and effectively occupies the area of just one transistor. Simulations have indicated read and write times of  10 ns. In principle, it is possible with this cell to have a retention time of > 10 years [2], enabling a non-volatile memory with ultra-low voltage operation to be realised. Transistor: The transistor is a vertical, fdy  depleted, double-gate SOI-MOSFET  (silicon-on-insulator  metal-oxide-semiconductor- field-effit-transistor)  with  barriers  in  the  channel  region,  as shown in Fig. 1. The gate voltage modulates the internal potential 848  ELECTRONICS LETTERS  13th May 1999  Vol. 35  No. IO in the intrinsic silicon region and the central shuffer barrier (CSB) or barriers also move  up and down  energetically following the internal potential. The CSB reduces the OFF current substantially, while  maintaining  a  high  device ON current. The  role  of  the source and drain barriers is to adjust the source impedance to the CSB  to  act  as diffusion  barriers keeping  a  low  impurity level within the channel, and to reduce the leakage current such as the gate induced drain leakage current at the drain side. -D+ source  source 7toxr  ?  /barrier 0 /  I "+:  drain insulator  barrier 6 drain Fig. 1 Stacked tunnel transistor A = dD2  18 +  DtozCsi  /2&szo2  (1) and E~,~~  are dielectric constants of silicon and silicon dioxide, respectively. TEM observation showed that the gate separation length D  was 0.045p1-1  as a result of over-etching the poly-Si, and U2h is estimated to be  1.2. From scaling theory, the same charac- teristics can be  obtained for 0.2~  gate separation length if the channel length is designed to be  200nm, and ideal subthreshold voltage swing of  OmVIdecade will be obtained in long channel transistors. -6 10 -9 a- io rn  - -12 10 Schematic cross-section of  transistor fabricated with  60nm channel length and triple tunnel barriers "GS," E3 Fig. 3 Measured drain currents at room temperature Inset: Subthreshold voltage swing against normalised channel length, comparing measured data and scaling theory SI  substrate  , 0.5  CI m  I Fig. 2 Transmission electron micrograph of transistor in Fig. I The transistors with triple tunnel barriers were fabricated on sil- icon dioxide using a standard 0.2~  silicon process, as shown in Fig. 2. All transistor regions, source, drain, channel, and gate, are made from polycrystalliie-silicon films. The thin tunnel junctions were formed by thermal nitridation of silicon; after deposition of the silicon layer, the surface of the silicon is directly converted to silicon nitride by heating at 900°C for 3min in a 100% NH,  ambi- ent. The thickness of the nitride is self-limited to -2nm with a bar- rier height of -2eV  [3]. The source and drain regions were heavily phosphorus doped to 2 x  102Oc1r-~,  and the channel region was maintained  at a  low  impurity level, lower than  lO~~crr-3  as con- fmed by  SIMS analysis.  The  gate was  boron  doped to  5  x lOI9cm3. The channel length L was 60 nm and the gate insulator was  formed  from 6nm of  silicon  dioxide. The  gate  separation width  D  was  0.2p1-1,  and  the gate width,  perpendicular  to the plane of Fig. 2, was 0.4~  on the optical photo-masks. Drain currents were measured against gate voltage for several drain voltages as shown in  Fig.  3.  The leakage current was  < O.lpA, which  is  the limit  of  our  measurement  system. A  sub- threshold voltage swing S of 96mVldecade was obtained, which is explained well by  the scaling theory for a double-gate SO1 MOS- FET [4]  as shown in  the inset of Fig.  3,  where h is the scaling length given by CCfF a  b  C rn Fig. 4 Cross-section of memory cell, equivalent circuit diagram and sim- ulated memory node voltages Vf' and  V"'  are in  read  cycle in  high  and  low  memory  states, respectively; %'La  and  Vja  are in storage cycle a Cross-section b Equivalent circuit c Simulated node voltages Gain cell: The transistor enables the construction of a novel high- density memory because  each memory cell  occupies the area of just one transistor, as shown in Fig. 4.  The transistor is stacked onto the gate of a conventional MOSFET with a built-in coupling capacitor for random access in  memory cell  arrays. High-speed writing is made possible by 'cooler' electrons transferred from the top electrode (bit line) onto the  storage node through the ON- state stacked transistor. Since the OFF-state stacked transistor can confine electrons very effectively, the  stored information can be kept for a long time without a refresh operation. Since the infor- mation is read through a MOSFET, this cell has gain and a large S/N ratio. The cell also has a high degree of immunity against soft errors because the essential memory section is small and isolated from the substrate, since there are no floating body effects as in partially-depleted  SO1  devices,  and  because  the  tunnel barriers restrict the separation of electron-hole pairs. ELECTRONICS LETTERS  13th May 1999  Vol. 35  No. IO  849 The gain cell consists of a stacked transistor, a sense MOSFET, and  a  built-in  coupling capacitor as shown  in  Fig.  4. Storage, read, and write cycles are all controlled by voltage V, on the word line,  VLq  (-2V),  VF) (0.5V), and  Vkw  (3V),  respectively. In the storage cycle the built-in capacitor Cc leads to the memory node voltage being  lower  than  the  threshold voltage  V,  of  the sense MOSFET. In the read  cycle  the memory  node voltage becomes higher than  V,,  when the memory state is high and lower than V, when the memory state is low. In the write cycle the stacked tran- sistor is opened, and the memory node voltages become the bit line voltages, 1.5V for the high memory state and OV  for the low memory state. Using the transistor characteristics of  Fig. 3, for a mixed-level device, a circuit simulation for a lOns read/write cycle was performed, and the memory node voltage  VN  was  calculated as a function of coupling capacitance Cc (Fig. 4). Random read access  in  the cell  arrays is  possible  when  V,  is  set  inside the hatched area, for example, between 0.5 and 45V  at a coupling capacitance of 0.04fF.  This coupling capacitance can be  realised for a 50nm thick storage node, without needing to form an addi- tional capacitor. Thus a memory cell size as small as 41“ where I; is the minimum feature size may be realised. The stored charge is determined by the gate capacitance of the sense MOSFET, and estimated to be  0.2fC. Although the drain- source current in  the ON state of  a  stacked transistor is  small, -1p4,  high-speed writing can be realised because of the reduced stored charge. In fact, writing was performed within  Ins in this simulation. Conclusion: Stacked tunnel transistors have shown good current- voltage characteristics with extremely low leakage current. Using this stacked tunnel transistor, a new RAM gain cell can be con- structed with a one-transistor cell  size and with  lOns read/write times. In principle, the retention time can be  longer than 10 years in this cell, although several possible leakage mechanisms such as due to hopping conduction must be clarified. 0  IEE 1999 Electronics Letters Online No: 19990574 DOZ: 10.1049/eI:19990574 K. Nakazato and  H. Mizuta  (Hitachi Cambridge Laboratory, Hitachi Europe Ltd., Cavensish Laboratory, Madingley Road, Cambridge CB3 OHE, United Kingdom) K. Itoh  (Central Research Laboratory,  Hitachi  Ltd., 1-280  Higashi- Koigakubo, Kokubunji, Tokyo 185-8601, Japan) H. Ahmed  (Microelectronics Research Centre,  Cavendish Laboratory, Madingley Road, Cambridge CB3 OHE, United Kingdom) 9 March 1999 References 1  NAKAZATO, K.,  PIOTROWICZ, P.I.A.,  HASKO, D.G.,  AHMED, H.,  and ITOH, K.:  ‘PLED -  Planar  localised  electron devices’.  IEDM  97, 1997, pp. 179-182 YAMAGUCHI, K.,  and  SHIMADA, T.:  ‘Normally-off  PLED  (planar localised electron device) for  non-volatile memory’. VLSI  Symp., 1998 3  MOSLEHI, M.M., and  SARASWAT, K.c.:  ‘Thermal nitridation of  Si  and Si02  for VLSI’, ZEEE  Trans., 1985, ED-32, pp. 106-123 4  SUZUKI, K.,  TANAKA, T.,  TOSAKA, Y.,  HORIE, H.,  and  ARIMOTO, Y.: ‘Scaling theory  for  double-gate  SO1  MOSFETs’,  IEEE  Trans. Electron Dev., 1993, ED-40, pp. 2326-2329 2  MIZUTA, H., NAKAZATO, K., PIOTROWICZ, P.J.A.,  ITOH, K., TESHIMA, T., Asymptotic criterion for neutral systems with multiple time delays Chang-Hua Lien A delay-dependent criterion is  proposed to  guarantee asymptotic stability for uncertain neutral systems with  multiple time  delays. The  criterion provides  some  information as to  the  size of  time delays and is  expressed by two inequalities. An  example  is given to illustrate the result. Introduction: In recent years, the stability problem in  time delay systems has been  extensively investigated [l - 71.  This is due to theoretical  as well  as practical interests for system analysis and design, since many engineering systems have inherent delay prop- erties, such as nuclear reactors, rolling mills, ship stabilisation sys- tems and systems with lossless transmission hies [l - 31.  Delays frequently lead  to instability and are a  source of  oscillations in many  systems; for example, the trivial solution of  X(t) + 2x(t) = -x(t) is  asymptotically stable, but that of  neutral system  x(t) + 2x(t -  z)  = -x(t) is unstable for any positive delay T  [3]. Consider the linear system where x(t) E W, B,, B E  Wxn,  i = 0, ..., m.  The necessary and suf- ficient condition for the asymptotic stability of the system of eqn. 1 is that B = Zs  B, E  Wxn  is Hunvitz (stable). It is reasonable to consider that the system contains state delays rn k(t)  =  BOZ(t) +  B&(t -  7%)  t 2 0  (2) 2=1 where T,>  0, i = 1, ..., m.  Many delay-dependent criteria have been presented for evaluating the allowable delay magnitude for asymp- totic stability of time-delay systems [4 -  61.  In the real world, sys- tems  will contain some information about past derivatives of  a state [l -  3, 1.  The aim of  this Letter is to consider the delay- dependent criterion for the asymptotic stability  of uncertain neu- tral systems with multiple time delays. The notation used  throughout this Letter is as follows. For a matrix A, we  denote the standard Euclidean  norm  by  llAll,  the matrix measure by MA), and the determinant by det[A]. StabiZity analysk: Consider the following uncertain neutral system: k(t)  +  AA,k(t -  7%)  = Bo~(t)  +  B,z(~  -  7%) a=1  2=1 t 20  (3n) x(t)  = 4(t)  t E  [-7,O]  (3b) where x E W, x, is the state at time t defined by x,(s) := x(t+s), V s E [-z,  01,  z = ?  zl 2  0, with Ilx,lls  := -z$$ollx(t+8)11,  B, E  Wxn, i = 0,  1, ..., m,  are known matrices, AA,, i = 1. 2, ..., m,  are con- stant perturbed matrices, and $ E C is a given  initial function, where C is a set of all continuous functions from [-z,  01  to W. The following assumption is made for the system of eqn. 3 throughout this Letter: Al: There exist non-negative constants a,, i = 1, 2, ..., m,  such that Lemma I: For matrices AA,,  B, E Wxn  satisfying Al, . 11B,11]  < 1, then the operator D:  C -  W with D(xJ = x(t) + Xzl [AA?(t-z,)+B,  :-%,  x(s)&] is stable [l]. Proof of Lemma  I:  The characteristic equation of homogeneous equation fix,) = 0 is [a,  + z, m .  e-=‘*  + B,  .  fTz ezsds)] Note that VRez 2 0 Hence the condition Z:,  [a, + z,  . 11B,l1] < 1 implies  that all roots of eqn. 4  lie in the open left plane of complex plane z, i.e. a, := sup{Rez :det[A(z)] = 0)  < 0. This completes the proof in view of [l], theorem 9.3.5.  0 We now present a delay-dependent criterion for the asymptotic stability of the system of eqn. 3. 850  ELECTRONICS LETTERS  13th May 1999  Vol. 35  No. 10 

Silicon stacked tunnel transistor for high-speed and high-density random access memory gain cell

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