Arai, T.

Kimura, Y.

Matsuda, S.

Mizuta, Hiroshi

Momo, N.

Nagami, T.

Oda, S.

Saito, S.

Shimada, T.

Tsuchiya, Yoshishige

English

Southampton (e-Prints Soton)

Fabrication and characterization of nanoscale suspended floating gates for NEMS memory  Nobuyuki Momo1, Tasuku Nagami1, Shinnosuke Matsuda1, Yoshishige Tsuchiya1,4, Shinichi Saito2,  Tadashi  Arai2, Yoshinobu Kimura2, Toshikazu Shimada2, Hiroshi Mizuta3,4,*, and Shunri Oda1,3,4  1 Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, 2-12-1, O-okayama, Meguro-ku, Tokyo 152-8552, Japan 2Central Research Laboratory, Hitachi Ltd., Tokyo, Japan   3Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan 4SORST, JST, Tokyo, Japan *Phone: +81-3-5734-2542 FAX: +81-3-5734-2542 E-mail: mizuta@pe.titech.ac.jp  Introduction Recent progress of silicon nanofabrication techniques has enabled not only to realize the MOSFETs with sizes of decananometer but also to explore a new field of silicon Nano Electro-Mechanical Systems (NEMS). We proposed a new non-volatile memory device concept based on a mechanically-bistable floating gate (FG) suspended in the cavity, which incorporates nanocrystalline Si (nc-Si) dots (Fig.1)[1]. We have already succeeded in fabricating a  3-µm-large suspended SiO2 beam with mechanical bistability[1]. In this paper we report on fabrication of various suspended FG structures with a top control gate. We also analyze the mechanical stress caused by the buckled FG by using Micro Raman Scattering Spectroscopy. Fabrication of the double layered floating gate We examined fabricating the double layered structures consisting of the suspended FG (without nc-Si dots) and the control gate by using both bulk-Si and SOI for substrates (see Fig. 2). For the bulk-Si substrate we first oxidized the Si substrate surface and deposited amorphous Si on the SiO2 and then performed SPC(Solid Phase Crystallization). We oxidized the poly-Si surface again and deposited a-Si , SiO2 and Cr sequentially to make the Si/SiO2/Si/SiO2/Si/SiO2/Cr stacked structure. For the SOI substrate we took the same processe above except the first oxidation, a-Si deposition and SPC. The same device fabrication processes were used for the both wafers after the stacked structures were prepared. Control gate patterning was performed by using EB lithography and Cr etching. For fabricating the upper and lower cavities, we adopted two different dry etching. The top SiO2 layer was patterned by anisotropic etching with the control gate as a mask, and then the underneath Si sacrifice layer was etched out by using isotropic etching which have a high Si/SiO2 etching selectivity. By repeating the same etching process, we fabricated the upper and lower cavities. For the both layered structures we succeeded in fabricating the double layered structures and observed both upward and downward bent FGs (Figs. 3 and 4). However, we also observed a remarkable difference in the shape of the bent FGs for the two structures in Figs. 3 and 4. For the SOI based structures (Fig.4), bending was seen only across the beam part. On the other hand, for the poly-Si based structures (Fig. 3), the pad area supporting the beam was also deformed in addition to the beam bending. We also noticed that about 90% beams showed the upward bending for the SOI based samples while the poly-Si based samples show completely random bending (50% upward and 50% downward). It is likely that the structural difference found here is caused by whether the SiO2 beam was fabricated by oxidizing bulk-Si(SOI) or poly-Si. From the stand-point of device design, the SOI based beam with good structural control is preferred, and we therefore adopted it in the following experiments. We finally fabricated the double layered structure with the FG which contains the nc-Si dots. The FG layer was made by performing SOI oxidation, nc-Si deposition and SiO2 deposition. We succeeded in fabricating the nc-Si embedded FG structure as shown in Fig.5. We found that the degree of bending is slightly smaller for the nc-Si embedded FG structure than that for the reference structure without the nc-Si dots. We also found that the nc-Si embedded FGs exhibit only the upward bending. This is presumably caused by the different mechanical properties of the top SiO2 deposited onto the nc-Si dots. This hypothesis was confirmed by the AFM observation that showed surface roughness of the top SiO2 due to the embedded nc-Si dots. Mechanical stress characterization Next we characterized the mechanical stress caused by the suspended FG by using Micro Raman Scattering Spectroscopy. When either tensile or compressive stress is applied to Si, Si Raman frequency shifts from its stress-free value. The relation between the shift of Raman frequency and the stress is given as follows [2], ] [cm 434 [MPa]-1 ω σ ∆ =  where  0 > ∆ω for tensile stress and  0 < ∆ω for compressive stress. We scanned a 5µm×5µm area on and around the beam part every 1µm step. We prepared three different FG samples: (a) without underetching, (b) half underetched and (c) fully underetched. The sample without underetching did not show any remarkable stress distribution. The half and fully underetched samples, however, showed tensile stress of about 100MPa around both ends of the beams (Fig.6). These results are qualitatively consistent with the stress distribution calculated by using the 3D FEM mechanical simulation (Fig. 7).   Summary We succeeded in fabricating the double layered structure    which have the suspended FG and the control gate. We compared the difference in the geometry of the SOI-based and poly-Si-based FGs and found superior structural controllability for the SOI-based structures. Based on these findings we finally succeeded in fabricating the double layered structure with the FG which contains the nc-Si dots. We also characterized the stress distribution around the suspended FG for the first time by using Micro Raman Scattering Spectroscopy. References [1] Y.Tsuchiya et al., Abstr.of Si Nanoelectronics Workshop, p.101 (2004) [2]    Ingrid De Wolf,    J. Raman Spectrosc. 30, 877, (1999)   Fig.1: A schematic illustration of a NEMS memory device   Fig.2: Process steps of double layer structure   Fig.3: Double layer structure using poly-Si   Fig.4: Double layer structure using SOI   Fig.5: Double layer structure with nc-Si   Fig.6: Stress distribution of fully underetched sample   Fig.7: Stress distribution calculated by using 3D FEM simulation. Only a quarter of the whole structure is shown. 

Abstr.of Si Nanoelectronics Workshop,

Fabrication and characterization of nanoscale suspended floating gates for NEMS memory

Fabrication and characterization of nanoscale suspended floating gates for NEMS memory

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