CORE
CO
nnecting
RE
positories
Services
Services overview
Explore all CORE services
Access to raw data
API
Dataset
FastSync
Content discovery
Recommender
Discovery
OAI identifiers
OAI Resolver
Managing content
Dashboard
Bespoke contracts
Consultancy services
Support us
Support us
Membership
Sponsorship
Research partnership
About
About
About us
Our mission
Team
Blog
FAQs
Contact us
Community governance
Governance
Advisory Board
Board of supporters
Research network
Innovations
Our research
Labs
research
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder
Authors
M Balakrishnan
RCC Cheung
MK Jaiswal
K Paul
Publication date
1 January 2014
Publisher
'Institute of Electrical and Electronics Engineers (IEEE)'
Doi
Cite
Abstract
postprin
Similar works
Full text
Open in the Core reader
Download PDF
Available Versions
Crossref
See this paper in CORE
Go to the repository landing page
Download from data provider
info:doi/10.1109%2Ftcsii.2014....
Last time updated on 20/06/2021
HKU Scholars Hub
See this paper in CORE
Go to the repository landing page
Download from data provider
oai:hub.hku.hk:10722/248403
Last time updated on 21/11/2017