A low power 64-point FFT/IFFT architecture is developed for the application in OFDM based wireless broadband communication system. The proposed architecture satisfies the specifications of IEEE 802.11a and ETSI Bran. The architecture requires 25% multiplication and 86% addition/subtraction operation compared to the conventional Cooley-Tukey approach. This leads to power and area saving as well. The architecture is capable to perform FFT and IFFT without changing the internal coefficients which makes it highly suitable for practical applications

Grass, Eckhard

Jagdhold, Ulrich

Maharatna, Koushik

English

Southampton (e-Prints Soton)

Thus, the 64-point FFT can be computed by firsttaking 8-point FFT of the appropriate data slot(described in equation (3)) then multiplying themwith 8 intedimensional constants and once againtaking 8-point FFT of the resultant data.The  IFFT  can  be  performed  by  firstswapping  the  real  and  imaginary  parts  of  theincoming data and then performing the forwardFFT on them and once again swapping the realand imaginary parts of the data at the finale. Thismethods allows one to perform the IFFT withoutchanging  any  internal  coefficients  and  thus,resulting  into  more  efficient  hardwareimplementation.3. Architectural descriptionThe basic architecture of the proposed 64-point FFT/IFFT module is shown in Figure 1. Itutilizes  two  input  buffers,  one  8-point  FFTmodule, an internal buffer and four multipliers.According to the specification IEEE 802.11a andETSI  Bran,  the  FFT  block  receives  the  dataevery 4 msec for duration of 3.2 msec. in serialmanner. To satisfy this constraint, we used twoinput  buffers.  The  input  data  slots  are  storedalternately in these buffers and the 8-point FFTmodule switches from one buffer to another tofetch new set of data as soon as the computationof  64-point  FFT  for  a  particular  data  slot  iscompleted.After  computation  of  first  8-point  FFT  onthe initial input data sequence, the resultant dataundergoes  the  interdimensional  constantmultiplication operation. The multiplied data arestored  in  an  internal  register  ‘cb’  (shown  inFigure 1) from where they are rerouted to the 8-point  FFT  module  in  appropriate  order  togenerate  the  final  result.  The  final  results  arestored in the buffer cb once again from where theoutput is generated in serial manner.The  input  mechanism,  the  internalcomputation  process  and  the  data  outputmechanism are carried out in pipelined fashion.The parallelism and pipelining introduced in thisarchitecture  is  favorable  from  the  powerconsumption point of view.To  perform  the  FFT  and  IFFT  using  thesame architecture, we introduce a signal ‘mode’.The  logic  LOW  state  of  mode  implies  theforward  FFT  operation  while  its  logic  HIGHstate enables one to perform IFFT operation.Two  additional  signal  ‘data_valid’  and‘data_next’ are kept that indicate input valid dataand output valid data respectively. These signalsare  important  from  the  point  of  view  of  theintegration of the  complete  wireless  broadbandcommunication systems. They indicate valid dataoperation condition to the previous and the nextblock  of  the  system.  Thus,  this  FFT/IFFTprocessor  can  be  utilized  as  the  stand-aloneprocessor  or  it  can  be  integrated  with  otherrequired components to form a complete system.4. Performance of the architectureFrom  the  algorithmic  point  of  view,  theproposed  architecture  requires  less  number  ofarithmetic computations compared to that of theconventional  Cooley-Tukey  algorithm.  This  isshown in Table 1.Algorithm ComplexMultiplicationAddition /subtractionCooley-Tukey[3]192 1152Proposed 49 994Table 1. Comparison of the number of arithmeticoperations with the Cooley-Tukey algorithmThe above comparison shows that the proposedarchitecture  requires  25%  real  multiplicationcompared to that of the conventional approach.In terms of the number of addition, the proposedarchitecture requires 86% of those required in theconventional  approach.  This  results  intosignificant reduction of power dissipation.The architecture is first coded in VHDL andthen simulated using Mentor graphics’ Quicksimsimulator. For convenience, the simulation resultof FFT for a pure cosine function input is shownin  Figure  2(a).  The  result  of  IFFT  on  theresulting data is shown in Figure 2(b) that showsthe  functional  correctness  of  the  architecture.The  architecture  is  synthesized  for  0.25mmCMOS technology at 20 MHz clock  frequencyusing  Synopsis  Design  Analyzer  tool.  Thesynthesized  circuit  is  simulated  using  Mentorgraphics’  Modelsim  simulator  that  once  againexhibits  the  correctness  of  the  structure.  Thesynthesis result shows that the area consumptionof the complete FFT structure is 4.9 mm2 that isequivalent  to  81.666K  inverter  count  at  thattechnology.  At  the  operating  frequency  of  20MHz  the  power  consumption  of  the  wholestructure  is  78.5169  mW.  At  20  MHz  clockfrequency  the  core  architecture  is  capable  tocompute  64-point  FFT/IFFT  within  2.8msec.However, with the serial input and serial outputcircuitry,  it  completes  the  computation  of  thePre-print of 5th OFDM workshopFigure 2(a). The simulation result for FFT on a pure cosine wave input.Figure 2(b). The simulation result for IFFT on the data of Figure 2(a).

10), “Broadband Radio Access Networks (BRAN);

An algorithm for the machine calculation of complex Fourier series”,

A low-power 64-point FFT/IFFT architecture for wireless broadband communication

A low power 64-point FFT/IFFT architecture is developed for the application in OFDM based wireless broadband communication system. The proposed architecture satisfies the specifications of IEEE 802.11a and ETSI Bran. The architecture requires 25 % multiplication and 86% addition/subtraction operation compared to the conventional Cooley-Tukey approach. This leads to power and area saving as well. The architecture is capable to perform FFT and IFFT without changing the internal coefficients which makes it highly suitable for practical applications

K. Maharatna

E. Grass

U. Jagdhold

CiteSeerX

Figure 2 (a).1.  Input for the FFTFigure 2 (a).2.  Output of the FFTFigure 2 (b).1.  Input for the IFFTFigure 2 (a).2.  Output of the IFFTFigure 3.  Power consumption of the processor over differentclock cycles0102030405060701471013161922252831343740434649525558616467707376798285Clock cyclesPower consumption (mW)

http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.332.3835

A Low-Power 64-point FFT/IFFT Architecture for Wireless Broadband Communication

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