Enhanced performance is demonstrated from a buried, compressively strained-Si0.7Ge0.3 p-MOSFET fabricated on a relaxed Si0.85Ge0.15 using a high thermal budget 0.25 µm CMOS process. The devices are designed to be fully compatible with a strained-Si CMOS process but offers a number of potential benefits over a surface channel p-MOSFET for certain circuit applications. Transconductance, on-current, hole velocity and mobility enhancements are observed over surface strained-Si channel devices on both Si0.85Ge0.15 and Si0.8Ge0.2 virtual substrates and the bulk Si control devices for constant effective channel length. The buried channel devices exhibit enhancements over the Si control devices of 93% in on-current and 62% in hole velocity for 0.25 µm effective channel length devices without compromising the subthreshold characteristics. The extracted effective mobility for the buried channel device is over 40% greater than the universal mobility curve for bulk Si p-MOS devices at 0.55 MV/cm vertical effective electric fields. Index Terms—CMOS, p-MOSFET, strained-Si, SiGe, quantum well, thermal budget, drain current enhancements, transconductance enhancements, virtual substrate

Cerrina, Claudia

Evans, Alan G.R.

Li, Xiabbing

Olsen, Sarah H.

O’Neill, Anthony G.

Paul, Douglas J.

Tang, Yue T.

Temple, Matthew P.

Waite, Andrew M.

Zhang, Jing

English

Southampton (e-Prints Soton)

IEEE TRANS. ELEC. DEV., VOL. X, NO. X, JANUARY 2004 3compressive strain. A second issue is that a tensile strained-Silayer grown on a relaxed Si1−yGey buffer is higher in energyto holes than the relaxed substrate [9][10]. This combinedwith the lower effective mass in the vertical direction resultsin a larger spread of the wavefunction into the substratecompared to electrons. It can result in a parasitic channel ofholes in the relaxed Si1−yGey buffer especially if high Gecontents in the substrate are used to improve the mobility sincethen only a thin strained-Si channel can be grown under thecritical thickness. Therefore the use of a buried, compressivelystrained-Si1−xGex quantum well may have advantages inimproving the hole mobility in such devices by the use ofthe lower effective mass and by conﬁning the holes away fromthe Si/SiO2 interface [7][18]. The mobility enhancement in thestrained-Si surface p-MOSFET has been limited to less than30% for standard virtual substrates with Ge contents of 20%and below [13][15] with silicon-on-insulator devices requiredfor any signiﬁcant mobility improvement [17][19].A number of papers have demonstrated the higher mobilitypossible in compressively strained SiGe quantum wells eitherin p-MOSFETs or modulation-doped FETs but all have usedlow thermal budget processing [20][21][22]. In particulardeposited gate insulators rather than a thermal gate oxide havefrequently been used [20]. We have previously demonstratedthe performance of strained-Si n-MOS transistors fabricatedon top of a buried Si0.7Ge0.3 layer with a Si0.85Ge0.15 virtualsubstrate and processed using a high thermal budget 0.25 µmCMOS process [14]. Signiﬁcant performance enhancementswere demonstrated over bulk Si devices. Very little perfor-mance degradation was demonstrated with the addition of theburied Si0.7Ge0.3 layer to the strained-Si n-MOS devices. Wehave also demonstrated improved strained-Si p-MOS enhance-ments with high thermal budget processing using low energyplasma enhanced chemical vapor deposition virtual substrates[23]. In this paper we demonstrate p-MOS transistors with acompressively strained buried Si0.7Ge0.3 channel, grown ona Si0.85Ge0.15 virtual substrate and processed using the samehigh thermal-budget CMOS process as the n-MOS devices[14]. Enhanced performance over control Si devices of Ion,transconductance, hole velocity and mobility are observed fora large range of effective channel length devices. The extractedeffective mobility for the buried channel device is over 40%greater than the universal mobility curve for bulk Si p-MOSdevices at 0.55 MV/cm vertical effective electric ﬁelds.II. DEVICE DESIGN AND FABRICATIONThe wafers were grown by low pressure chemical vapordeposition on 100 mm n-type (18-33 Ω-cm) (100) siliconsubstrates [24]. The process gases of Si2H6 and GeH4 wereused with AsH3 as the n-type dopant. Virtual substrates weregrown at 800 oC with the active regions grown at 550 oC toreduce Ge diffusion. Typical growth parameters can be foundin [24]. The virtual substrates consisted of 1.5 µm gradedSiGe followed by 1 µm of constant composition Si1−yGeydoped with As to 1017 cm−3 with Ge contents of y=0.15 and0.20. The temperature was then reduced to 550 oC beforea constant Ge composition undoped spacer of 50 nm wasFig. 1. The drain-current as a function of source-drain voltage for gateoverdrive voltages of 0.5, 1.5 and 2.5 V. All devices have a lithographic gatelength of 0.3 µm and 5 µm width and all measurements are dc.then grown followed by the channel layers. The thickness ofthis spacer layer was chosen after modelling the As diffusionduring the high thermal budget fabrication process to producea retrograde doping proﬁle for the n-type wells. N-type dopantdiffusion of As and P in SiGe is known to be larger than thatin bulk Si [25] but there is little accurate data in the literaturefor the diffusivity of n-type dopants in SiGe. Therefore thesetback of the dopant was modeled using diffusion data forSi [26]. All process steps with thermal anneals above 400 oCwere included in the diffusion modeling. Simulations indicatethat a 50 nm spacer will result in a channel doping of less than1016 cm−3 whilst providing good subthreshold characteristics.On the Si0.85Ge0.15 virtual substrate a 20 nm i-Si layer wasgrown and a 17 nm i-Si on the Si0.8Ge0.2 virtual substrate.Both these tensile strained-Si layers are below the Matthewsand Blakeslee critical thickness [27] and should therefore bestable to high temperature processing [28][29]. The buriedchannel device was grown on top of a Si0.85Ge0.15 virtualsubstrate and consisted of a 50 nm undoped Si0.85Ge0.15spacer, a 10 nm undoped compressively-strained Si0.7Ge0.3channel and a 10 nm undoped tensile-strained Si cap. Thiscap thickness was chosen after a number of simulations tocalculate the consumption of the cap through cleans, thermaloxide growth and also Ge diffusion [30] from the Si0.7Ge0.3channel. At least 2 nm of Si cap should remain after thedevices have been processed. This is especially important asany Ge incorporated into the oxide would create defect statesor result in Ge pileup at the SiO2 interface increasing theinterface trapped charge density and reducing the transistorperformance [31][32].Device fabrication followed the process ﬂow of a high-thermal budget 0.25 µm CMOS process [14][23]. Si controlwafers were also processed after the n-well was implantedusing a three stage phosphorus implant of 4×1012 cm−2 doseat 400 keV, 2×1013 cm−2 dose at 280 keV and 2×1012 cm−2dose at 70 keV. Modelling was used to design the well implantto be nominally identical to the well doping in the as-grownheteroepitaxial material. It should be noted that Si wafers withepitaxially grown doping proﬁles demonstrated near identicalperformance to the present Si control implanted well wafers[33]. No chemical mechanical polishing (CMP) of the startingIEEE TRANS. ELEC. DEV., VOL. X, NO. X, JANUARY 2004 4Fig. 2. The subthreshold plots for the Si control, strained-Si on Si0.8Ge0.2and buried channel devices. All devices have a lithographic gate length of 0.3µm and 5 µm width.substrates at any stage was undertaken as previous resultshave demonstrated signiﬁcantly higher mobilities [14][23] thanCMP polished substrates[13][20]. As CMP is likely to produceoff-cut surfaces when the growth and relaxation processes areconsidered [34], non CMP substrates should be expected toproduce higher mobilities [35]. A thermal gate oxide wasgrown at 800 oC followed by an anneal in a N2 atmosphere.Source and drain implants using high doped drain (HDD) andlow doped drain (LDD) structures with Si3N4 spacers wereactivated with a 1020 oC rapid thermal anneal and a fulltitanium salicide process was used. Oxide thicknesses of 4.5nm were extracted from C-V characteristics of 300×300 µmMOS capacitors.III. ELECTRICAL RESULTSFig. 1 shows the measured drain current, Ids as a functionof source-drain bias Vds for as-drawn 0.3 by 5 µm (Lg byW) devices at three values of gate overdrive |Vg − Vt| whereVg is the gate voltage and Vt is the threshold voltage. On-current enhancements are observed for each of the strained-Si devices including the buried channel over the bulk Sicontrols. At |Vg − Vt| = −Vds = 2.5 V, Ids for the strained-Si surface channel device on Si0.85Ge0.15 exceeds that ofthe control by 50%, whereas for the strained-Si device onSi0.8Ge0.2 the enhancement is 60%. The enhancements arehigher at lower gate overdrive (|Vg − Vt| = 1.5 V) due tothe result of reduced self-heating in the strained-Si devices[36] since only dc measurements of devices are presented inthis paper. It is apparent from Fig. 1, however, that the currentdrive performance is considerably lower for the buried channeldevice than for the surface channel strained-Si devices. Idsenhancements of the buried channel device over the Si controlof 38% at -1.5 V and 21% at -2.5 V are observed.The subthreshold Ids versus |Vg − Vt| characteristics for thesame strained-Si (20%), buried channel and control devicesare plotted in Fig. 2. All the devices exhibit on-current/off-current ratios of at least seven orders of magnitude, suggesting,together with the extracted values of subthreshold slope, Sthat electrostatic integrity is not seriously compromised in thestrained-Si devices. The strained-Si and buried channel devicesFig. 3. The effective channel length as extracted by the shift and ratiotechnique versus the drawn or lithographic gate length for the 4 differentwafers.actually have better subthreshold slopes that the Si controldevices.IV. EFFECTIVE CHANNEL LENGTHThe plotting of performance parameters as functions oflithographic gate length, Lg, however, can be misleadingespecially for submicron LDD MOSFETs. In such cases,the effective channel length Leff is normally taken as theindependent variable rather than Lg in comparing channel-length dependent performance parameters [37]. Particularly inLDD structures, the lateral straggle in the source and draindoping can actually cause Leff to increase signiﬁcantly withrespect to Lg, as can a retrograde, setback or modulationdoping proﬁle [37]. Furthermore, Leff may exhibit a strongdependence on gate bias at low gate overdrives |Vg − Vt|because of the virtual channel which forms in the LDD regionsunder or close to the gate contact [38]. The diffusivities ofdopants in strained-Si and SiGe are expected to be higherthan in bulk Si especially for the p-type implant boron usedfor the Ohmic contacts [39], possibly leading to differentLDD and HDD source and drain proﬁles and hence differentmetallurgical as well as effective channel lengths. Leff iseffectively a measure of the length over which a gate biascan invert charge in the substrate to form a channel, and isalso found to be sensitive to the doping proﬁle perpendicularto the channel; it is found to be signiﬁcantly longer thanthe metallurgical gate length in the case of retrograde doping[37] and for buried channel Si pMOSFETs [40]. In ﬁg. 3 Lgis plotted against Leff for the Si controls and the surface-and buried-channel strained-Si devices. The shift and ratiomethod for Leff extraction was used and is described in detailelsewhere [23][37]. For the shortest channel length devices,Lg is longer than Leff for the strained-Si surface channeldevices, as expected from enhanced source and drain diffusion,compared with the controls. For the buried channel devices,Leff is indeed signiﬁcantly higher by approximately 0.2 µm,as anticipated.Replotting Fig. 1 for a constant Leff of 0.25 µm is shownin Fig. 4. For Leff of 0.25 µm, the buried channel devicenow has higher performance than the surface strained-Si p-

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Compressively-strained, buried-channel $Si_{0.7}$ Ge $_{0.3}$ p-MOSFETs fabricated on SiGe virtual substrates using a 0.25 µm CMOS process

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Compressively-strained, buried-channel Si0.7Si_{0.7}Si0.7​Ge0.3_{0.3}0.3​ p-MOSFETs fabricated on SiGe virtual substrates using a 0.25 µm CMOS process

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Compressively-strained, buried-channel $Si_{0.7}$ Ge $_{0.3}$ p-MOSFETs fabricated on SiGe virtual substrates using a 0.25 µm CMOS process