This paper discusses a small. seven and a half (7.5) inch diameter. satellite that NASA-JSC is developing as a technology demonstrator for an astronaut assistant free flyer. The Free Flyer is designed to off load flight crew work load by performing inspections of the exterior of Space Shuttle or International Space Station. The Free Flyer is designed to be operated by the flight crew thereby reducing the number of Extra Vehicle Activities (EVA) or by an astronaut on the ground further reducing crew work load. The paper focuses on the design constraint of a small satellite and the technology approach used to achieve the set of high performance requirements specified for the Free Flyer. Particular attention is paid to the processor card as it is the heart and system integration point of the Free Flyer

Abbott, Larry

Jochim, David

Schuler, Robert

NASA Technical Reports Server

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A vionics For A Small Satellite 
Dr. Larry Abbott, David Jochim, Robert Shuler 
NASA-1SC, 2101 NASA Road I, Houston, Texas, 77058 
28 1-483-8593, labbott @ems.jsc.nasa.gov 
Source of Acquisition 
NASA Johnson Space Center 
Abs tract - Th is paper discusses a small. seven and a half (7.5) inch diameter. sate ll ite th at NASA-JSC is developing as 
a technology demo nstrato r fo r an astronau t ass istan t free flye r. The Free Fl yer is designed to off load fl ight crew work 
load by performing inspections of the exterior of Space Shutt le or International Space Slation. The Free Flyer is 
desi gned to be operated by the fl ight crew thereby reducing the number of Extra Vehicle Activit ies (EVA ) or by an 
astronaul on the grou nd fu rther reducing crew work load . The paper focuses on the design constraint of" small sate litc 
and the.: ll:chnology approal..h used to achieve the et of high performance requirements specified fo r the F: ,-c Flye r. 
Particul ar attent ion is paid to the processor card as it is the heart and system integration point of the Free Flyer. 
INTRODUCTION 
In 199_ NASA flight tested a free fl yer called "Sprint". Sprint was thirteen (13) inches in diameter and 
used a 1 MIPS processor with 32Kbytes of memory to perform simpl ified , integer fli ght contro l laws. 
Sprint also provided a propulsion system, dual analog video and uplink/downlink capability. 
It is an irony that as technology improves, system requirements increase just enough to offset the ga in in 
technology. The technology available in 2000 allows a smaller Sprint to be easily developed, but the 
requirements for the second generation of the Astronaut assistant Free Flyer far exceed those of Sprint Not 
only must the size be reduced to a seven and a half inch sphere, but Sprint 's simplified integer control laws 
are being replaced with sophisti cated , fl oating point control laws, position hold is to be added, and digital 
GPS filtering is being added to the processor load. Sprint 's two analog cameras are bei ng replaced with 
three digital camera's and accompanyi ng video compress ion capability, Sprint ' s propulsion system is being 
replaced with a harmonized propulsion system, and Sprint batteries are being replaced wi th Li-ion 
technology. All the above technologies rely, to varyi ng degrees, on the power of the new processor. 
Design Constraints 
Although the requirements fo r the free flyer have grown, the physics of space fl ight and the vo lume of the 
seven inch sphere dictate that the power, mass, and of course vo lume can not grow. In fac t it is preferable 
that power and mass be reduced. 
TABLE 1. Compari son of Power, Weight, & Volume 
Constraints Sprint Free flyer 
Power 20 watts 18.2 1 watts 
Weight 35.5 Ibm 10.38 Ibm 
Volume 11 50 in) 65.95 in) 
There are several major design constrai nts that dri ve the internal config uration and packaging of the Free 
Fl yer vehicle. In part ic ul ar, the placement and confi gurat ion of the av ionics are dri ven by the size, shape, 
and thermal characteri stics of the vehicle she ll. 
The spherica l vehic le geo metry req uired fo r a "safe" vehic le impac ts every facet of subsystem des ign. Fi rst 
of all , the spherica l pac kaging vo lume poses strict dimensional and geometri c constrai nt s on indi vidual 
components. [n addi tion, the Free Fl yer packaging vo lume has been reduced over 80% from the Sprint 
vehic le while functional capabi lity has been significantl y increased. This large dec rease in internal vo lume 
and surface area for ht:a t rejec tio n naturall y leads to a ve hicle wi th a much higher packaging effic iency and 
to concerns about local anu bulk thermal stabi lity. 
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https://ntrs.nasa.gov/search.jsp?R=20100042638 2019-08-30T13:45:05+00:00Z
L __ 
Upper Hcmi -Spheri ca l 
I of I Thruster Pods 
2 of 12 Thrusters 
Center 
Structual 
Ring 
Figure 1: External View of Free Flyer (Left) and cutaway view (Right) 
Preventing individual components from exceeding their specified temperature limits is a major packaging 
challenge for thi s vehic le . The vehicle ' s high power and small s ize, coupled with its operationa l thermal 
environment, make it prone to localized overheating. Current vehicle architecture does not include acti ve 
cooling for thermal conditioning. Therefore, it is extremely important that the packaging account for heat 
fl ow through and away from the vehicle. Preliminary analysis has shown that steady state bulk average 
temperatures sho uld not exceed component operational limits even in the worst-case environments. The 
bulk thermal temperature is highly dependent on operati onal scenario and environment, both of which can 
be readily altered if temperatures become marginal. Therefore, the temperature will be monitored. Analysis 
and Sprint fli ght experience shows that loca lized temperatures can exceed the bulk average temperature by 
40 degrees Fahrenheit. The design locates major heat sources away from the avionics and close to the outer 
radiating surfaces. 
Getting hea t away fro m the boards and to the vehicle radi ati ng surfaces is the second issue to be addressed . 
The avionics utili zes high efficiency DCIDC switching converter to reduce power consumption and waste 
heat. The converters are mounted on the top side of the processor board where thermal transfer foam and 
direct contact to a metallic plate transfers heat way from the converters and the processor board directly to 
the o uter shell. The processor board transfers additional heat to a thermal strip on the outer edge of the 
borard which also has a thermal interface to the outer structure. Proxi mity to other radiation heat sources is 
also a concern. Therefore di stributing the heat sources around the ball and as far from each other becomes 
important. Adjacent heat sources inc lude the batteries, a GPS receiver, and a video compression card. 
Each of these components is similarl y provided with a direct heat path to the outer she ll and should not 
significantly contribute to heating of the av ionics . 
Given the fact that the Free Flyer has a higher packing density, accessibi lity is a significant problem. To 
address accessibi lity, the primary structure and internal configuration has been simpli fied . T he power and 
propulsion systems occupy the center structural ring, communications and GNC occupy the top 
hemisphere. and avionics occupies the lower hemisphere. Each of these systems is accessible 
independentl y from the rest si mpl y by removing o ne of the hemispheres. 
Unfort unate ly. the requirement that the hea t generat ing components be di stri buted fo r therma l reasons 
makes the physical connec ti vi ty to the processor diffic ult. Connect ion between subsyste ms will be 
managed by routing wi re-runs from the subsystems into and a long the perimeter of the central ring and then 
into the processor board . Proper management of these numerous wire-runs wi ll assure desired 
accessibi lit y. 
[-
Technology 
Putting all the performance required for the Free Flyer into a seven and a half (7 .5) inch sphere requires 
state-of- the-art (SOA) technology, but even given SOA technology. Over the last twenty years, improving 
technology has usuall y meant designing more performance into electronics compo nen ts, which in turn 
packs more performance into the same size, weight and power package. When memory density quadruples 
the package is not cut to one quarter size; rather the package size remains the same and the amount of 
memory is quadrupled. As a result, processors get faster and memories get denser, but the size of the 
packages stays roughly the same. Therefore it has been difficult to control vol ume and mass with silicon 
technology alone. This is particularly true for minimal systems like the Free Flyer, since the opportunity for 
combining 4 or even 2 items into one item doesn ' t exist, i.e. combining four banks of memory into 1 higher 
density bank. 
The integrated circuit packaging techno logy played the largest role in reducing the size and weight of the 
Free Flyer 's avionics. On the Free Flyer, most of the weight and volume gains came from much denser 
packing of the integrated circuit boards and the almost exclusive use of Surface Mount Technology (SMT) 
to allow both sides of the circuit board to be populated. 
Improved chip design does reduce the power consumption of chips through the increased use of low power 
technologies such as CMOS and reduced power consumption sleep modes. In the case of the Free Flyer 
versus Sprint, the improved processor technology produces a high performance PowerPC which is 
projected to be awake less than 10% of the time. As a result of spendi ng 90% of the time spent in sleep 
mode, the Free Flyer processor compares favorably with the Sprint's 1 MIPS processor in terms of power 
consumption while still producing nearl y fifty (50) MIPS . The SDRAM memory, while much larger in 
terms of bits than Sprint's SRAM, consumes much less power on a bit for bit basis. Due to these 
improvements in processor and memory technology the Free Flyer's performance far exceeds Sprint's 
performance while its avionics is roughly the same size and consumes roughly the same power. 
ARCHITECTURE 
The Free Flyer's avionics architecture went through a series of evolutionary stages to meet its 
requirements. In the first stage NASA sought not on ly to retain as much of its investment in the UMC [1,2] 
as possible, but to retain as well , the modularity and re-use philosophies built into UMC through its use of 
the PC-104 bus standard. In its initial stage the arch itecture was envisioned as a stripped down version of 
the PC-104 used on the UMC. The adaptability and universality of the standard PCI and ISA buses were 
sacrificed to reduce power and space. Instead, the processor's Front Side Bus (FSB) was extended for use 
as a local bus interface to external periphera l functions. The size of the stackable cards reduced and the 
size of the corresponding connectors were reduced. However, early in the design it became apparent that 
the operational requirements would not allow everything to fit onto neat little rectangular cards organized 
in an orderly stack. The stack was rejected because of the needs of the various systems, such as 
propulsion, GPS and UplinkIDownlink antennas, and video, to be located in specific locations within the 
vehicle. 
As the operationa l requirements forced changes to the architectural concept, at first the extended FSB was 
supplemented with serial buses to those parts of the architecture that could not be located adjacent to the 
Processor Card. In the next stage, the use of the extended FSB for external interfaces to the Processor Card 
was abandoned altogether. Instead , all peripherals, adjacent or not, connect to the processo r card via serial 
buses. In the final stage, modular, re-usable rectangular cards were abandoned, and as much of the adjacent 
avionics as possible was integrated onto a single, circular processor card for overa ll packaging efficiency 
and the rmal transfer reasons. The remaining avionics is interfaced to the processor cards through serial 
buses. The use of the extended FSB as an external interface is gone, and now the processor's FSB connects 
directly and exclusively to the FPGA. The FPGA in turns implements the functionality of the memory 
controller, interrupt controller, timers, serial ports, and memory and thruster interfaces. 
Data&Status 
Video(2.7 Mbps) 
plink(CM D&Contro l) 
----~ 
Downlink(Data&Status) 
Thruster 
MD&Control 
Hub 
Processing, Memory, 
Data tribution, 
Data Bus, 
Thruster Driver 
Power conversion. 
Volts ,Current. 
Figure 2 : STAR architecture for free flyer 
On many levels the architecture has evolved into a star architecture, with the processor card is at the hub of 
the new architecture. The processor, memory, and serial buses are on the hub , thus making the architecture 
a star in terms of data. and command and control. The processor card is also a star in terms of vehic le 
secondary power because all of the vehicle's DCIDC conversion is also in the hub. 
The Processor 
The need to minimize power consumption while retaining a high performance, floating point capability 
demands a processor with a high MIPS to watt ratio and the abi lity to scale the MIPS and therefore the 
power to the problem at hand. The PowerPC provides this capability. The predecessor to the Free Flyer' s 
processor, the UMC processor card, has a 166 MIPS 603e, 8 Mbytes Flash, 32 Mbytes SDRAM, PCI bus, 
and ISA bus. It consumes 4 watts at 100% capability and 1.3 watts when it is in sleep mode. The removal 
of the ISA and PCI buses and the associated bridge from will offset the increased power consumption from 
the upgrade to the PowerPC 750. The incorporation of the rest of UMC's functionality into the processor 
board 's FPGA (with the except of the clock generation and reset circuitry) is expected to actually reduce the 
po wer consumption below UMC levels. At 3 times the MIPS, the PowerPC 750 will be in sleep mode 
much more than would have been the case for a 603e based design further reducing the power 
consumption. In addition to the power consumption advantages of the PowerPC, radiation hardened 
versions of the 603e and 750 are nearing availabi lity. 
The design approach fo r the project requires flexibility and developer friendliness to be designed into the 
engineering pro tot ype. Later. in the port of the fully developed engineering prototype to the flight article, 
achieving radiatio n to lerance and lowest power will beco me more important. At that time the 
reprogrammable FPGA used fo r the engineering prototype will replaced with a suitable lo w power, 
radiatio n tolerant. fu sible link FPGA that will become avail able in the summer o f2001. 
Glue Logic 
& Clock 
PowerPC 
Processo 
Global Clk Bus 
FPGA 
LVDS 
LVDS 
C&T Downlink Video Channel 
C&T Downlink Channel 
C&T Uplink Channel 
LED CMD/Data 
Camera Data 
'-100 ___ ..... Camera Cmd Channel 
Instrumentation 
GFE Data 
GFE CMD Channel 
GPS CMD/Data Channel 
TBD 
Figure 4: The processor 
FPGA 
The FPGA used on the free flyer is in fact quite large, but it is input/output (VO) bound; not logic bound. It 
must provide the 72 bit wide SDRAM controller function, the Hamming code EDAC function, the interrupt 
controller function, the Flash memory interface, L VDS serial ports , legacy serial ports (for ground support 
equipment and integrated circuits with existing interfaces), thruster dri ver logic , timers, and counters. 
Unique among these functions is the thruster driver logic which fires the thruster continuously for 4 msec . 
In order to reduce power consumption any thruster firing beyond initial 4 msec is performed with a 25 % 
duty cycle, 1 kHz square wave. A watchdog time (WDT) is provided to protect against continual, non 
commanded firings . Finally the harmonized thruster controls require precise and variable firing periods 
over a large range of firing durations. Initially this requirement as expressed as a need for a 4 msec minor 
cycle that would allow the thruster firing to be extended or terminate every 4 msec. This would allow 
indefinite thruster firing with 4 msec resolution, albeit with an unacceptable overhead placed on the 
processor. Once the control problem was fully understood by all disciplines, the thruster driver was 
modified to allow variable firing times of2 to 100 msec in 1 msec steps. Not only did this solution offer 
finer firing duration resolution, but the minor cycle was relaxed to 40 msec. This relaxed minor cycle 
allows the processor to spend more time in the sleep mode which in turn reduces the over all power 
consumption of the processo r. 
The thrusters require at least 20 volts for proper operation and the batteries require 29.4 volts at the 
beginning of their discharge cycle to meet the 20 volts requirement at the end of a four hour mission. 
Initially MOSIS techno logy was to be used to reduce the space taken by the twelve, high side thruster 
drivers, however the 29.4 vo lts battery requirements exceeds the MOSFET breakdown voltage available 
Thruster Dri ver 
using stardard MOSIS processing. For a time the thruster dri ver design reverted to a di screte compo nent 
imple mentatio n. Later. it was realized that the thruster drivers could meet the 29.4 vo lt requirement with 
the standard MOSIS processing techno logy if the drivers were fabricated with MOSFETs arranged in 
series . In addition. the MOSIS dri vers are to be implemented with a NASA developed radiation tolerant 
design that will allow radiation tolerant devices to be fabricated with the standard MOS IS processing 
technology. To date the techno logy has been tested with 200 Mev Pro tons and the test chips have passed 
exposure of 19 krads and 51 krads. Duri ng the testing there have been no observed latch ups and no 
observed SEUs. 
Read Status Cmd 
Thruster Status • 
to Processor • 
Vi a FPG A • 
• 
ClearWDT 
CMOs from 
Processor 
Firing Durarion 
Data 
Reference List 
• 
• 
• 
• 
• 
• 
• 
• 
WDT inhibits thn"ot • .,.<nfr..,. 
Current/no_current 
status from other 
removesinhibit and clears WDT count when 
the Fire Thruster CMD is removed 
4 msec 100% duty cycle cmd is only present during the 
initial 4 msec of firing. Firing cmd'ed in subsequent 
minor cycles shall be at 25% duty cycle if firing 
is continued. 
Figure 6: FPGA Thruster Driver Function 
SUMMARY 
[I J Abbo tt. Larry W .. Gary Cox . Ha i Hguyen. Adapting PC/I 04 fo r Space. PC I 04 EmbeddedSolutions. 
Summer 2000. Volume 5 Number 2, Fountain Hills . Arizona, Open Systems Publishi ng, pages 33-
40, www.pl:I04-cmhcuucu-so lns .com. 
[21 Abbott, La rry W .. Gary Cox. Hai Hguyc n. A Cos t Effcc tive System Design Approach for Critical 
Space Systems. 191h Digita l Avionics System Conferencc. October 7-13. 2000, Ph il adelphia. Pa. 
I 
J 


Avionics for a Small Satellite

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