Amorphous Co:Si (1:2 ratio) films are electron gun-evaporated on clean Si(111), such as in a molecular beam epitaxy system. These layers are then crystallized selectively with a focused electron beam to form very small crystalline Co/Si2 regions in an amorphous matrix. Finally, the amorphous regions are etched away selectively using plasma or chemical techniques

Fathauer, Robert W.

Lin, True-Lon

Nieh, Kai-Wei

English

NASA Technical Reports Server

United States Patent I191 1111 Patent Number: 5,075,243 
Nieh et al. [451 Date of Patent: Dec. 24, 1991 
FABRICATION OF NANOMETER SINGLE 
CRYSTAL METALLIC COS12 STRUCTURES 
ON SI 
Inventors: 
Assignee: 
Appl. No.: 
Filed: 
Kai-Wei Nieh, Monrovia; True-Lon 
Lin, Cerritos; Robert W. Fathauer, 
Sunland, all of Calif. 
The United States of America IS 
represented by the Administrator of 
the National Aeronautics and Space 
Administration, Washington, D.C. 
677,373 
Mar. 27,1991 
Related U.S. Application Data 
Continuation of Ser. No. 392,166, Aug. 10, 1989, aban- 
doned. 
Int. C l . 5  ........................................... HOlL 21/265 
US. Cl. ...................................... 437/40, 437/973; 
437/935; 437/942; 437/907; 437/200; 
148mIG. 46; 148/DIG. 48; 148/DIG. 154 
Field of Search ................. 437/40, 907, 970, 973, 
437/935,942,200; 156/628; 148/DIG. 46, 
DIG. 48, DIG. 154 
[561 References Cited 
U.S. PATENT DOCUMENTS 
4,554,045 11/1985 Bean et al. ................ 156/DIG. 102 
4,555,301 11/1985 Gibson et al. ............ 156DIG. 102 
4,755,256 7/1988 Ditcheck .................... 156/DIG. 73 
4,855,014 8/1989 Kakimoto et al. .................. 156/603 
4,897,150 1/1990 Dooley e: al. ...................... 156/628 
4,816.421 3/1989 Dynes et al. .......................... 437/25 
Primury Examiner-Brian E. Hearn 
Asvistunr Exuminer-Trung Dang 
Attorney, Agent, or Firm-Thomas H. Jones; Harold W. 
Adams; John R. Manning 
L571 ABSTRACT 
Amorphous &:Si (1:2 ratio) films (12) are electron 
gun-evaporated on clean Si(] 11) substrates (lo), such as 
in a molecular beam epitaxy system. These layers are 
then crystallized selectively with a focused electron 
beam (14) to form very small crystalline CoSin regions 
(12‘) in an amorphous matrix. Finally, the amorphous 
regions are etched away selectively using plasma or 
chemical techniques. 
16 Claims, 1 Drawing Sheet 
IO 
https://ntrs.nasa.gov/search.jsp?R=19920009319 2020-03-24T07:10:36+00:00Z
U.S. Patent Dee. 24, 1991 
Fig. 1. 
5,075,243 
Fig. 2. 
IO 
Fig. 3. 
5,075,243 
1 2 
hereinafter when taken in conjunction with the follow- 
ing figures which accompany it. FABRICATION OF NANOMETER SINGLE 
CRYSTAL METALLIC COS12 STRUCTURES ON SI BRIEF DESCRIPTION OF THE DRAWINGS 
ORIGIN OF THE INVENTION 
The invention described herein was made in the per- 
formance of work under a NASA contract, and is sub- 
ject to the provisions of Public Law 96-5 17 (35 U.S.C. 
202) in which the Contractor has elected not to retain 
5 FIGS. 1-3 are cross-sectional views of a silicon sub- 
strate which is processed in accordance with the teach- 
ings of the invention. 
DETAILED DESCRIPTION O F  THE 
INVENTION .- 
The fabrication of structures with lateral dimensions 
on the order of nanometers is extremely difficult. Spe- 
tions, particularly for dimensions below 100 nm (0.1 
' 5  pm). Applications of such structures in the case of met- 
als include quantum wires and dots, and gates and other 
features for various transistors, including MESFETs 
and MOSFETs. In addition, use of a metallic layer as an 
electron-beam resist would allow transfer of the nanom- 
The method described herein allows the fabrication 
title. 
This is a continuation of co-pending application Ser. 
No- 07/392,166 filed on Aug. 10, 1989, now abandoned. cial ttchniques are required, dl of which have 
TECHNICAL FIELD 
The invention relates to transistors and other struc- 
tures having lateral dimensions on the order of nanome- 
ters, and, more particularly, to a method for fabricating 
such structures. 
BACKGROUNDART 20 eter- c scale pattern to non-metallic materials. 
Modification of the microstructure of thin films by of metallic with extremely small lateral di- energy beams has studied' mensions. The metallic Structures are formed On a sub- 
beams and lasers have been for rapid surface heat- strate, which may comprise any material, such as silicon 
Ion beams at energies Of lo to IO3 KeV have been 25 or other semiconductor or oxide thereof (e.g., silicon 
amorphous. Other well-known substrate materials, such 
invention, 
phous State on the surface of the substrate. While the 
amorphous material specifically disclosed herein is co- 
tallintion are also 
to thin processing as surface dioxide), whether single crystalline, polycrystalline, or 
heating, ion-implantation, and ion mixing. 
number of thermally activated processes, including 
films, diffusion of gold in amorphous silicon, and epihx- 
ial growth of amorphous silicon on crystalline silicon. 
solid strongly. Generation of point defects by high-en- 
ergy electrons in various semiconductors has been re- 35 The deposition of the amorphous Structure is 
tron induced amorphization of alloys have been studied. such as molecular beam epitaxy. ne amorphous strut- 
However, due to its small mass, the electron is not effec- ture is deposited in the stoichiometry of the final crys- 
tive in displacing atoms as ions. The effect of electron 4o h]lized structure. 
irradiation on the microstructure of thin films has not ne amorphous structure is converted to a crystalline 
been extensively studied. metallic structure by exposure to an electron beam at 
Increasingly small structures are required for a vari- the appropriate energy and dose. For example, amor- 
ety Of microelectronic devices. There are currently no phous a : S i  layers crystallize at rmm temperature 
techniques which readily allow fabrication of structures 45 under an electron beam. Selectivity in the etching rates 
with the desired dimensions for several applications. of amorphous and single-crystal a S i 2  may then be 
exploited to remove .the amorphous regions, leaving 
quantum wires and dots or other features on a silicon 
substrate. This processing sequence is shown schemati- 
vide a method for fabricating small structures having 5o cally in FIGS. 1-3. 
lateral dimensions on the order of nanometers. In particular, FIG. 1 illustrates a silicon substrate 10 
It is another object of the invention to provide a having formed thereon a layer 12 of amorphous cobalt- 
method for fabricating small-scale structures in semi- :silicon (Q:Si), deposited in the stoichiometric ratio of 
conductor devices. 1:2. The amorphous Q:Si layer 12 is deposited to a 
It is yet another object of the invention to provide a 55 thickness of about 10 to 1,ooO A. The thickness is dic- 
method for fabricating small-scale gates in silicon field tated by penetration of the layer by electrons without 
effect transistors (FETs). Significant loss of energy. 
Briefly, in accordance with the invention, a portion A focused electron beam 14 is then directed onto the 
of an amorphous film deposited on a substrate is crystal- surface of the Co:Si layer 12. By focused is meant the 
Iized to form either a single crystal portion or a p l y -  60 smallest possible beam size available with the e-beam 
beams have been used to enhance a as &F2, may also be employed in the practice of the 
grain growth of polycrystalline and germanium 30 The metallic Structure is initially formed in the amor- 
Electrons, king charged particles* jnteract with the balt:silicon, other materials capable of controlled cry+ 
by the invention. 
ported. Electron radiation damage On metals and achieved by any ofthe well-known deposition methods, 
STATEMENT O F  THE INVENTION 
Accordingly, it is an object of the invention to pro- 
crystalline portion, by exposure of the portion to an 
electron beam. The amorphous regions remaining are 
then removed, leaving behind the crystallized portion, 
which is of sub-micrometer lateral dimension, and with 
appropriate electron beam size, may approach nanome- 65 
ter dimension. 
Other objects and benefits of the invention will be- 
come apparent from the description which follows 
equipment. In the discussion herein, that beam size is 
200 nm; beam sizes as low as 5 nm are presently avail- 
able. 
The effect of the electron beam is to induce epitaxial 
growth in the exposed region. As seen in FIG. 2, that 
portion 12' of the amorphous &:Si layer 12 exposed to 
the electron beam is converted into single-crystal 
Cosiz. 
5,075,243 
3 
The amorphous &:Si layer 12 is then removed, as 
shown in FIG. 3, leaving the single-crystal structure on 
the silicon substrate. Thus, it will be readily appreciated 
that a resistless process is provided. 
The technique of solid phase epitaxy of an amorphous 
CoSi (1:2) layer allows the formation of epitaxial &Si2 
on Si( 11 1) at very low temperatures. The stoichiometric 
ratio of the amorphous deposit is the key to obtaining 
low temperature formation, as it prevents the formation 
of intermediate silicide phases (as is observed for the 
more conventional silicide formation method of react- 
ing a metal layer into a silicon substrate). We have ob- 
served the presence of very small single-crystal regions 
in amorphous Co:Si (1 :2) layers. Under TEM observa- 
tion at room temperature, the regions grow laterally to 
yield single-crystal epitaxial CoSh regions of greater 
extent. 
By using a focused electron beam, we have success- 
fully fabricated 300-nm-wide single crystal &Si2 lines 
in a 10-nm-thick C0:Si amorphous matrix on a sili- 
con(l11) substrate. Bright-field and dark-field TEM 
micrographs have been taken of a planar section of the 
sample, where the characters “CoSi2” were crystallized 
in the amorphous layer. In one case, a &Si* diffraction 
spot was used to form the image, so that only the single- 
crystal CoSiz regions appeared bright. The epitaxial 
growth of the CoSi2 was induced by a 300 keV electron 
beam with an emission current of 10 pA in a Philips 430 
scanning TEM. We find that the epitaxial &Si2 is 
sharply confined in the electron-beam bombarded area, 
with the amorphous C O S  unchanged 10 nm away from 
the beam. 
These results imply that selective crystallization in an 
electron-beam lithography system will be possible. 
Such systems have typical spot sizes of approximately 8 
nm, which would allow the formation of structures of 
single-crystal material with dimensions down to 28 nm 
or less. (The value of 28 nm is obtained by adding the 
8-nm spot size to IO-nm mentioned above for each side 
of a line.) It should be noted that electron-beam lithog- 
raphy with resist technology is limited to approximately 
40 nm minimum features. 
The single-crystal CoSis structures would be embed- 
ded in the surrounding amorphous &:Si. The amor- 
phous C O S  could be removed selectively using a suit- 
able etching technique. We have found that amorphous 
&:Si (1:2) is eJched by, HF:H20 (1:9) at a rate of ap- 
proximately 3 A/sec. Single-crystal CoSi2, on the other 
hand, is attacked by this same solution much more 
slowly, by at least an order of magnitude. This selectiv- 
ity is adequate for the purpose of removing the amor- 
phous Co:Si without adversely affecting the singletrys- 
tal CoSi2. (Several other chemical or dry etching tech- 
niques would probably also be suitable.) Single-crystal 
metallic structures may thus be fabricated on a silicon 
substrate. 
In order to obtain crystallization of a portion 12 of 
the amorphous layer 12, the energy of the electron 
beam must be at least about 100 keV, and preferably 
about 200 to 300 keV. If the energy is higher than this, 
the electrons will pass through the layer 12 into the 
substrate 10, still crystallizing the portion 12’, but possi- 
bly not as much as at the indicated preferred range. 
An alternative method to achieve crystallization em- 
ploys electron beam energy at a level of less than 100 
keV, and preferably in the range of about 20 to 50 keV. 
The preferred range is easily achievable with the elec- 
tron beam apparatus commercially available for use 
4 
with electron beam resist technology. While this alter- 
native method is certainly useful, it is not as preferred as 
operating at the higher energy range, since it relies on 
heating to achieve the crystallization. Such heating is on 
5 the order of 150” C., and results in broadening of the 
exposed portion 12‘ by about 5095, ih contrast to the 
higher energy exposure, which evidences essentially no 
broadening. 
The dose rate is at least about 1021 cm-lmin-1; less 
10 than that rate results in an unacceptably slow growth 
rate. At the indicated dose rate, crystallization proceeds 
at a lateral rate of a few Angstroms per minute. Higher 
dose rates correspondingly result in higher crystalliza- 
tion rates. 
The portion 12’ is exposed to the electron beam 14 for 
a period of time to effect complete conversion of the 
portion 12, to single crystal (or polycrystalline mate- 
rial). Under the conditions disclosed above (energy of 
about 300 keV and dose of 1Ocm-Imin-I), about five 
20 minutes exposure is sufficient to convert the amorphous 
&:Si to crystalline cobalt silicide. 
There are a number of potential application of this 
technology. One of these is the fabrication of fine wires 
and dots exhibiting quantized confinement of carriers. 
25 Such structures will probably require dimensions of a 
few tens of nanometers or less (sub-micrometer dimen- 
sions). There has been no clear demonstration of these 
structures to date, but they are expected to exhibit novel 
conduction and optical absorption properties. 
The method of the invention is not necessarily limited 
to single-crystal silicon substrates. For example, if an 
insulating substrate were desired, epitaxial CaF2 on 
silicon would likely prove suitable. In addition, poly- 
crystalline CoSi2 with small dimensions would be 
35 formed on polycrystalline silicon, Si02 or other materi- 
als. This could find application in submicrometer-gate- 
length transistors (such as MESFETs or MOSFETs) as 
a gate electrode. While the etching rate of polycrystal- 
line CoSi2 is expected to be faster than that of the single- 
40 crystal material, it is still expected to be several times 
slower than amorphous material. 
Finally, the CoSiz may be used as an electron-beam 
resist. Our preliminary results indicate that smaller di- 
mensions may be achievable using this technique than 
45 can be realized with photoresist techniques. The pat- 
terned CoSi2 could be used as a mask to etch underlying 
materials. Etching tekhniques which do not readily 
attack CoSi2 would be required. Examples are plasma 
etching in CF. and chemical etching in dilute HF:H2O 
While the formation of crystalline cobalt silicide is 
discussed above, other amorphous materials, such as 
Ir:Si, may be similarly crystallized. The determination 
of such materials is not considered undue experimenta- 
55 tion; deposition of the material under conditions to form 
an amorphous structure at the appropriate stoichiome- 
try and exposure to an electron beam under the condi- 
tions discussed above will readily reveal whether the 
material is suitably employed in the practice of the 
Thus, metallic features, such as CoSi2 are formed on 
a substrate, having sub-micrometer lateral dimensions. 
It will be appreciated by those skilled in the art that 
various changes and modifications of an obvious nature 
65 may be made without departing from the spirit and 
scope of the invention, and all such changes and modifi- 
cations are considered to fall within the scope of the 
invention as defined by the appended claims. 
15 
30 
50 or phosphoric acid. 
60 invention. 
5.07 5.243 
5 
We claim: 
1. Method for forming features on a substrate, said 
features having sub-micrometer lateral dimensions com- 
prising: 
(a) forming an amorphous coating on said substrate, 
said amorphous coating comprising a material ca- 
pable of controlled crystallization; 
(b) exposing a portion of said material to a focussed 
electron beam for a period of time and with suffi- 
cient electron energy and dose to crystallize said 
portion, said electron energy ranging from about 
20 to 300 keV, while maintaining said coating at a 
temperature ranging from room temperature to 
150" C., the lower temperatures being associated 
with the higher electron energies; and 
(c) removing all amorphous coating remaining, leav- 
ing said crystallized portion on said substrate. 
2. The method of claim 1 wherein said substrate com- 
p r i m  a material selected from the group consisting of 2o 
silicon, silicon dioxide, and CaF2. 
3. The method of claim 2 wherein said amorphous 
coating comprises a material selected from the group 
consisting of cobalt:silicon and iridium:silicon. 
coating consists essentially of coba1t:silicon in an atomic 
ratio of Co:Si of 1:2. 
5. The method of claim 4 wherein said crystallized 
portion comprises CoSi2. 
6. The method of claim 1 said electron energy ranges 30 
from about 200 to 300 keV and said coating is main- 
tained at about room temperature. 
7. The method of claim 1 wherein said electron en- 
ergy ranges from about 20 to 50 keV and wherein said 
8. The method of claim 1 wherein said dose is at least 
4. The method of claim 3 wherein said amorphous 25 
elevated temperature is about 150" C. 35 
about l@l cm-lmin-1. 
6 
9. The method of claim 1 wherein said substrate com- 
prises silicon, said amorphous coating comprises COS,  
deposited in a stoichiometric ratio of 1:2, and said crys- 
tallized portion comprises CoSi2. 
10. A method for fabricating field effect transistors 
having submicrometer gate lengths comprising: 
(a) forming a polycrystalline coating on a layer of 
silicon dioxide, said polycrystalline coating com- 
prising a material capable of controlled crystalliza- 
tion; 
(b) exposing a portion of said material to a focussed 
electron beam for a period of time and with suffi- 
cient electron energy and dose to convert said 
portion to a single crystal portion, said electron 
energy ranging from about 20 to 300 keV, while 
maintaining said coating at a temperature ranging 
from room temperature to 150' C., the lower tem- 
peratures being associated with the higher electron 
energies; and 
(c) removing all polycrystalline coating remaining, 
leaving said singlecrystal portion on said substrate. 
11. The method of claim 10 wherein said polycrystal- 
line coating comprises cobaksilicon. 
12. The method of claim 11 wherein said polycrystal- 
line coating consists essentially of coba1t:silicon in an 
atomic ratio of @:Si of 1:2. 
13. The method of claim 12 wherein said single-crys- 
tal portion comprises CoSi2. 
14. The method of claim 10 said electron energy 
ranges from about 200 to 300 keV and said coating is 
maintained at a temperature of about 150" C. 
15. The method of claim 10 wherein said electron 
energy ranges from about 20 to 50 keV and wherein said 
elevated temperature is about 150" C. 
16. The method of claim 10 wherein said dose is at 
least about 1021 cm-Imin-1. * * * * *  
40 
45 
50 
55 
65 


Fabrication of nanometer single crystal metallic CoSi2 structures on Si

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