A high voltage multijunction solar cell comprises a number of discrete voltage generating regions, or unit cells, which are formed in a single semiconductor wafer and are connected together so that the voltages of the individual cells are additive. The unit cells comprise doped regions of opposite conductivity types separated by a gap. The method includes forming V-shaped grooves in the wafer and orienting the wafer so that ions of one conductivity type can be implanted in one face of the groove while the other face is shielded. A metallization layer is applied and selectively etched away to provide connections between the unit cells

Chai, A. T.

Evans, J. C., Jr.

Goradia, C. P.

English

NASA Technical Reports Server

United States Patent [191 
Evans et al. 
[54] HIGH VOLTAGE V-GROOVE SOLAR CELL 
[75] Inventors: John C. Evans, Ravenna; An-Ti Chai, 
N. Ridgeville; Chandra P. Goradia, 
Cleveland, all of Ohio 
represented by the Administrator of 
the National Aeronautics and Space 
Administration, Washington, D.C. 
[73] Assignee: The United States of America as 
[21] Appl. NO.: 359,388 
[22]* Filed: Mar. 18, 1982 
Related U.S. Application Data 
[62] 
[5 11 
[52] 
[58] 
[561 References Cited 
Division of Ser. No. 219,678, Dec. 24, 1980, Pat. No. 
4,335,503. 
Int. Cl.3 ............................................. HOlL 31/06 
U.S. C1. ....................................... 136/249; 357/30 
Field of Search ........................... 136/249; 357/30 
U.S. PATENT DOCUMENTS 
3,150,999 2/1961 Rudenberg et al. ................ 136/256 
3,278,337 8/1962 Gault ................................... 136/255 
3,969,746 12/1973 Kendall et al. ..................... 357/255 
4,135,950 1/1979 Rittner ................................ 136/255 
[I11 4,376,872 
[45] Mar. 15, 1983 
4,166,919 9/1979 Carlson ............................... 136/257 
4,200,472 4/1980 Chappell et al. .................... 136/246 
4,283,589 8/1981 Kaplow et al. ..................... 136/249 
4,323,719 4/1982 Green .................................. 136/249 
4,330,680 5/1982 Goetzberger ....................... 136/247 
4,341,918 7/1982 Evans, Jr. et al. .................. 136/249 
Primary Examiner-Aaron Weisstuch 
Attorney, Agent, or Firm-N. Musial; J. Manning; G. 
Shook 
P71 ABSTRACT 
A high voltage multijunction solar cell comprises a 
plurality of discrete voltage generating regions, or unit 
cells, which are formed in a single semiconductor wafer 
(10) and are connected together so that the voltages of 
the individual cells are additive. The unit cells comprise 
doped regions of opposite conductivity types (30, 32) 
separated by a gap. The method includes forming V- 
shaped grooves (16) in the wafer and thereafter orient- 
ing the wafer so that ions of one conductivity type can 
be implanted in one face (e.g., 16a) of the groove while 
the other face (e.g., 16b) is shielded. A metallization 
layer (22) is applied and selectively etched away to 
provide connections between the unit cells. 
8 Claims, 9 Drawing Figures 
https://ntrs.nasa.gov/search.jsp?R=19830023906 2020-03-22T01:20:07+00:00Z
U.S. Patent MU. 15, 1983 Sheet 1 of 2 4,376,872 
127- I 4an 14ah 
I \ I \ 
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n+lON FLUX 20 
2 
-16b FIG. I(d) 
f10 (12 
FIG. I(e) 
127 107 b 
U.S. Patent MU. 15, 1983 Sheet 2 of 2 4,376,872 
IO 
FIG. 2 
FIG. 3 
1 
HIGH VOLTAGE V-GROOVE SOLAR CELL 
4,376,872 
DESCRIPTION 
Origin of the Invention 
The invention described herein was made by employ- 
ees of the United States Government and may be manu- 
factured or used by or for the Government without the 
payment of any royalties thereon or therefor. 
Staement of Copendency 
This application is a division of application Ser. No. 
219,678 which was filed on Dec. 24, 1980 and issued as 
U.S. Pat. No. 4,335,503. 
Field of the Invention 
The present invention relates to an improved high 
voltage solar cell. 
BACKGROUNDART 
In our concurrently filed copending application Ser. 
No. 219,677, now U.S. Pat. No. 4,341,918, which is 
entitled "Planar Multijunction Solar Cells," and the 
subject matter of which is hereby incorporated by refer- 
ence, there is disclosed a new type of solar cell exhibit- 
ing a high output voltage. In brief, the solar cell in 
question comprises a multiplicity of voltage generating 
regions within a single semiconductor wafer, each of 
the regions forming a unit cell within the wafer and the 
unit cells being connected together in series so that the 
contributions of all of the cells are added together. 
Although the solar cell disclosed in the aforementioned 
application is obviously not limited to such a method, a 
specific exemplary method for making the planar multi- 
junction cell disclosed in that application provides for 
the creation of the voltage generating regions in a flat 
surface of the planar wafer by implantation or diffusion 
of active and passive materials to form p+, metal, and 
n+ regions within the flat surface. The implanting of 
metal creates certain problems. The present invention 
eliminates such implanting of metal and thus offers sub- 
stantial advantages as compared with the technique 
discussed above. 
Reference is made to the patents and other materials 
cited in the abovementioned patent for a discussion of 
other prior art techniques of possible interest. 
SUMMARY OF T H E  INVENTION 
In accordance with the invention a high voltage mul- 
tijunction solar cell of the type discussed above is pro- 
vided. More particularly, a solar cell comprising a plu- 
rality of discrete voltage generating regions or unit cells 
formed within a single semiconductor body or wafer 
are connected together so the voltage outputs of the 
individual unit cells are additive. As noted hereinbefore, 
metal implantation into the semiconductor body is elim- 
inated, and significant advantages over fabrication 
methods which require such metal implantation are 
obtained. 
According to the invention grooves are formed in the 
surface of a semiconductor body of one conductivity 
type, p or n, the grooves having first and second faces 
arranged at an angle to one another. An ion flux is used 
to implant ions of a first conductivity type into the first 
faces of the grooves so as to form doped regions of this 
first conductivity type therein while the semiconductor 
body is oriented such that substantially none of the ions 
are implanted into the second faces of the grooves. In 
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other words, doped regions of a first conductivity type, 
e.g., n+ or p+, are selectively implanted in one face of 
the grooves. In the next step, doped regions of the op- 
posite conductivity type are selectively formed in the 
second or other faces of the grooves, the semiconductor 
body being oriented during this step so that the first 
faces are protected and thus no ions of the opposite 
conductivity type are implanted therein. Thereafter, 
metallization is provided in the grooves over the doped 
regions so as to connect the doped regions together. 
The metallization in an individual groove serves to 
connect together two adjacent unit cells of which the 
two doped regions of the groove individually form part, 
a unit cell being formed by one doped region of one 
groove and an oppositely doped region of a second, 
adjacent groove and the two regions being separated by 
a gap therebetween. This gap can comprise an undif- 
fused portion of the semiconductor body between the 
two grooves which separates the two regions. 
The grooves are preferably V-shaped and in a spe- 
cific exemplary embodiment, the angle between the 
faces of a groove is 90" and the body is oriented at 45" 
and 135", respectively, during the two implantation 
steps. 
The metallization is preferably applied as a layer 
which covers one entire surface of the semiconductor 
body and selected portions of the layer are removed 
thereafter to provide the metallization between the 
grooves as well as contacts or terminals at the edges of 
the cell to enable the cell to be connected to an external 
circuit. A photoresist masking step followed by an etch- 
ing step is preferably used both in forming the grooves 
as well as removing the unwanted portions of the metal- 
lization layer. The semiconductor body is preferably 
coated with a metal oxide layer and all or substantially 
all of this layer is also removed with the removal of the 
unwanted metal. 
Other features and advantages of the invention will 
be set forth in, or apparent from the detailed description 
of the preferred embodiments which follows: 
BRIEF DESCRIPTION OF THE DRAWINGS 
FIGS. l(a) to l(g) illustrates sequential steps utilized 
in carrying out a preferred embodiment of the method 
of the invention; 
FIG. 2 is a perspective view of solar cell device con- 
structed in accordance with the method of the inven- 
tion; and 
FIG. 3 is an end view, partially broken away, of a 
further embodiment of a solar cell constructed in accor- 
dance with the method of the invention. 
DETAILED DESCRIPTION 
Referring to FIGS. l (a)  to lu> there is illustrated the 
basic steps of forming the high voltage V-groove p-i-n 
solar cell of the invention. It will be appreciated that 
while a basic nine step process will be described, varia- 
tions and modifications can be effected in these steps 
within the scope and spirit of the invention. 
In the first step, referring to FIG. l(u), a semiconduc- 
tor wafer 10 of one conductivity, such as a single crystal 
of n or p type silicon, is thermally oxidized or otherwise 
coated with a dielectric or insulating protective layer 
denoted 12. In an exemplary embodiment, wafer 10 has 
a thickness of about one hundred micrometers or 4 Mils. 
In the second step, which is partially illustrated in 
FIG. l(b), the wafer is coated on one surface with a 
3 
photoresist material indicated generally at 14, the mate- 
rial 14 is expoded through a pattern mask to ultraviolet 
light, the exposed pattern is developed and the unpo- 
lymerized photoresist material is dissolved away leav- 
ing parallel strip-like regions of photoresist material, 
denoted 14a, on the surface of wafer to enable con- 
trolled silicon etching in the unprotected areas denoted 
146. 
In the third step, illustrated in FIG. l(c), V-shaped 
grooves 16 are etched in the unprotected areas 146 
through the oxide layer 12 into the silicon wafer 10. In 
a specific exemplary embodiment, the etching gap, i.e., 
the width of areas 14b, is approximately 70 micrometers 
wide and the depth of the etch is approximately ten 
micrometers from the oxide surface 12. The faces 16a 
and 166 of each groove 16 form an angle of approxi- 
mately 90" and the spacing between grooves 16 is ap- 
proximately 25 micrometers or 1 mil. Standard silicon 
etchants such as mixtures of hydrofluoric, nitric and 
acetic acids may be used in carrying out the etching step 
in accordance with conventional practice. 
In step four, illustrated in FIG. l(d), p +  ions, e.g., 
boron ions, are implanted along one wall or face of each 
V-groove 16 by appropriately orienting the surface of 
the silicon wafter 10 in relation to the direction of the 
incident ions. As illustrated, the wafer 10 is oriented at 
an angle of about 45" so that the lines of p+ ion flux, 
indicated at 18, are approximately perpendicular to one 
set of the faces of the V-grooves, viz., faces 16a. The 
opposite walls or faces 166 of grooves 16 like parallel to 
the direction of the ion beams 18 and thus the p+  ions 
are not incident upon these surfaces. 
In the fifth step, illustrated in FIG. l(d), the wafer 10 
is again oriented at 45" but at an angle of 90" to the 
position for the fourth step. In this position the other 
faces or walls 16b of grooves 16 are implanted with n+  
ions, e.g., phosphorous ions. In this step the faces 16b 
which receive the n + ions are perpendicular to the n + 
ion beam, indicated at 20, and the p+  doped faces 16a 
lie parallel to the beam and hence are shielded. 
In the sixth step the entire grooved wafer surface is 
coated with a metal layer 22, as illustrated in FIG. 1 0. 
In a specific embodiment this surface is coated with 
vacuum deposited or sputtered aluminum to a thickness 
of several micrometers. 
In the seventh step, which is also illustrated in FIG. 
10, photoresist material, generally denoted 24, is selec- 
tively applied in the grooves and over the ends of the 
wafer face. The photoresist material is dried, exposed 
through a suitable mask, and developed and thereafter 
the unpolymerized material is removed to leave protec- 
tive strips 24a over the metallization layer 22 and pro- 
tective strips 24b at the opposite edges of wafer 20. 
In the eighth step, illustrated in FIG. l(g), the areas 
which are not protected by strips 24a, 24b are etched so 
as to remove all of the underlying metallization layer 22 
and to remove the underlying oxide layer 12 to a depth 
closely approaching the silicon of wafer 10. Stated dif- 
ferently, a portion of the oxide layer 12 may be retained 
(and this has advantages) but all of the metal must be 
removed to prevent shorting out of the unit voltage- 
generating regions. The resist plastic strips 24a, 24b are 
then removed. 
In the ninth and final step, the outermost grooves and 
connection tabs are "tinned" with solder to provide 
terminals for connection to the external circuit. 
Referring to FIG. 2, a perspective view of the fin- 
ished solar cell is shown, a portion of the cell being cut 
4,3 76,8 72 
4 
away to show details of the V-shape groove. As illus- 
trated, p+  regions 30 are formed in one face of each of 
the grooves 16 while n+ regions 32 are formed to the 
other face of each groove. The portions of metallization 
5 layer 22 remaining in the grooves 16 after the etching 
step are denoted 34 and provide a series connection 
between the p+  and n+  doped regions 30, 32. The 
"tinned" metal tabs or terminals are indicated at 36. 
Referring to FIG. 3, there is shown a detail of a por- 
10 tion of a further embodiment of a solar cell constructed 
which is generally in accordance with the method set 
forth above but which is modified with respect to the 
n+  collector region. The embodiment of FIG. 3 is 
similar to that shown in FIG. 2 and like elements have 
15 been given the same reference numerals with primes 
attached. A unit cell or voltage generating region is 
formed by a pair of doped regions 30 and 32' separated 
by a gap region 38 of unimplanted semiconductor mate- 
rial. The p+  region 32' of one unit cell is connected to 
20 the n+  region 30 of an adjacent cell by metallization 
34'. In the embodiment of FIG. 3, in contrast to that of 
FIG. 2, the n+  collector region 30' extends along a 
substantial portion of the surface of wafer 10'. In a pre- 
ferred embodiment, an approximate ratio of 1 to 8 is 
25 provided for the length of the p+  doped base region 32' 
of groove 16 relative to the length of the n+  doped 
collector region 30'. The length of the gap region 38 is 
about 25 micrometers in an exemplary embodiment 
where the bulk doping is p-type silicon, although it will 
30 be appreciated that, as provided for in the patent re- 
ferred to above, other semiconductors, and other di- 
mensions, can obviously be used. 
Although the invention has been described in relation 
to exemplary embodiments thereof, it will be under- 
35 stood by those skilled in the art that variations and 
modifications can be effected in these exemplary em- 
bodiments without departing from the scope and spirit 
of the invention. 
We claim: 
1. A high voltage multijunction solar cell of the type 
having a plurality of discrete voltage generating regions 
connected together; said solar cell comprising 
a single semiconductor body of one conductivity type 
having oppositely disposed surfaces, 
a plurality of V-shaped grooves in one of said sur- 
faces, each of said grooves being short of and 
spaced from the oppositely disposed surface and 
including first and second faces angularly disposed 
to each other, 
first doped regions of a first conductivity type in said 
first faces, 
second doped regions of a second conductivity type 
opposite said first conductivity type in said second 
faces, 
gap regions consisting essentially of undiffused re- 
gions of said semiconductor body located between 
pairs of oppositely disposed doped regions of adja- 
cent grooves, 
said gap regions providing electrical isolation 
means between adjacent unit cells, 
said pairs of oppositely disposed doped regions 
defining voltage generating unit cells, and 
means for connecting together adjacent ones of said 
unit cells so that their output voltages are additive. 
2. A high voltage multijunction solar cell as claimed 
in claim 1 wherein the first and second faces of each of 
said grooves are arranged at an angle of about 90" to 
one another. 
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4,3 76,872 
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3. A high voltage multijunction solar cell as claimed 
in claim 1 wherein the semiconductor body has a thick- 
ness of about one hundred micrometers. 
4. A high voltage multijunction solar cell as claimed 
in claim 1 wherein the width of each of the V-shaped 5 
grooves at the surface of the semiconductor body is 
about seventy micrometers and the spacing between the 
grooves is about twenty-five micrometers. 
5. A high voltage multijunction solar cell as claimed 
in claim 1 wherein the means for connecting the unit 10 
cells comprises 
metal connections in each of said grooves for electri- 
cally connecting the first and second doped region 
in series. 
of one the faces of each of the V-shaped grooves along 
a substantial portion of the surface of the semiconductor 
body toward the doped region of opposite conductivity 
type in the second face of the adjacent groove. 
7. A high voltage multijunction solar cell as claimed 
in claim 6 wherein the ratio of the length of the one 
doped region extending out of the one face of each 
groove to the length of the other doped region in the 
second face is about 8 to 1. 
8. A high voltage multijunction solar cell as claimed 
in claim 7 wherein the gap regions consist essentially of 
undiffused regions of the semiconductor body between 
the ends of the one doped regions and the second faces 
of the adjacent grooves, the length of each of said gap 
6. A high voltage multijunction solar cell as claimed 15 regions being about 25 micrometers. * * * * *  in claim 1 wherein one of the doped regions extends out 
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High voltage v-groove solar cell

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