A digital demodulator for converting pulse code modulated data from phase shift key (PSK) to non return to zero (NRZ) and to biphase data is described. The demodulator is composed of standard integrated logic circuits. The key to the demodulation function is a pair of cross coupled one shot multivibrators and which with a flip-flop produce the NRZ-L is all that is required, the circuitry is greatly simplified and the 2(v) times bit rate contraint can be removed from the carrier. A flip-flop, an OR gate, and AND gate and a binary counter generate the bit rate clock (BTCK) for the NRZ-L. The remainder of the circuitry is for converting the NRZ-L and BTCK into biphase data. The device was designed for use in the space shuttle bay environment measurements

Shull, T. A.

English

NASA Technical Reports Server

United States Patent r191 
Shull 
[54] DIGITAL DEMODULATOR 
I751 Inventor: Thomas A. Shull, Newport News, 
[73] Assignee: The United States of America as 
Va. 
represented by the Administrator of 
the National Aeronautics and Space 
Administration, Washington, D.C. 
[21] Appi. No.: 171,928 
[22] Fifed: Jul. 18, 1980 
[51] Int. c1.3 ............................................. H03K 13/24 
1521 U.S. €3. ............................................. 340/347 DD 
[58] Field of Search ................ 340/347 DD; 3291’1 IO, 
329/126, 1 0 4 ,  375/84,82 
1561 References Cited 
U.S. PATENT DOCUMENTS 
3,047,853 7/1962 Macho1 ........................ 340/34? DD 
3,970,945 7/1976 hnapp ................................... 375/83 
PSK 
[ I  11 4,313,103 
[u] Jan. 26, 1982 
Primary Examiner-Charles D. Miller 
Attorney, Agent, or Firm-Howard J. Osborn; John R. 
Manning; William H. King 
[571 ABSTRACT 
A digital demodulator for converting PCM data from 
PSK to NRZ-L and to Bi+-L. The demodulator is com- 
posed of standard integrated logic circuits. The key to 
the demodulation function is a pair of cross-coupled 
one-shot multivibrators 11 and 12 which with a flip-flop 
13 produce the NRZ-L. In order to generate Bi+-L, the 
PSK carrier is constrained to be 2’Vtimes the data bit 
rate. If NRZ-L is a11 that is required, the circuitry is 
greatly simplified and the 2N times bit rate constraint 
can be removed from the carrier. A flip-flop 15, an OR 
gate 14, and AND gate 16 and a binary counter 17 
generate the bit rate clock BTCK for the NRZ-L. The 
remainder of the circuitry is for converting the NRZ-L 
and BTCK into 3i4-L. 
7 Claims, 2 Drawing Figures 
18 / i  I I l l  u 
MULTIVIBRATOR 
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1 
DIGITAL DEMODULATOR 
ORIGIN OF THE INVENTION 
The invention described herein was made by an em- 
ployee of the US.  Government and may be manufac- 
tured and used by or for the Government for govern- 
mental purposes without the payment of any royalties 
thereon or therefor. 
BACKGROUND OF THE INVENTION 
The invention relates to a digital demodulator and 
more specifically concerns a digital demodulator that 
will convert pulse code modulated (PCM) data from 15 
phase-shift-key (PSK) to non-return-to-zero (NRZ-L) 
and bi-phase (Eli+-L) data. 
One of the experiments being developed by the Na- 
tion& Aeronautics and Space Administration for the 
Long Duration Exposure Facility is the Shuttle Bay 20 
Environment Measurements. The data gathered by this 
experiment is pulse code modulated for recording on 
magnetic tape. During different data-taking periods, the 
recorder is run at different speeds. In order to be com- 
patible with the changing bandwidth of the recorder, 25 
the data is allowed to digitally phase shift key a square 
wave carrier having three selectable frequencies. To 
test the SBEM experiment, a PCM demodulator is 
needed to convert the data from PSK to Bi4-L for 
It is therefore an object of this invention to provide a 
simple, inexpensive digital demodulator for converting 
pulse code modulated data from PSK to Bi4-L. 
Another object of this invention is to provide a digital 
demodulator for converting pulse code modulated data 35 
from PSK to NRZ-L. 
Other objects and advantages of this invention will 
become apparent hereinafter in the specification and 
drawings. 
SUMMARY OF THE INVENTION 
5 
10 
decommutation and display. 30 
40 
A pair of one-shot (monostable) multivibrators and a 
flip-flop perform the PSK to NRZ-L demodulation 
function. The one-shot muhivibrators are connected to 45 
the PSK input, one triggering on rising edges and the 
other on falling edges of the input. The onephot multi- 
vibrator output pulse widths are set to threefourths of 
the expected carrier period and are cross-coupled 
through their reset inputs so that if an input transition 5o 
causes either one-shot multivibrator to pulse, a transi- 
tion one-half a period later is ignored. By detecting 
which one-shot multivibrator is pulsed, the value of the 
data bit is determined. The outputs of the two multivi- 
brators are connected to the set and reset inputs of the 55 
flip-flop for this purpose. The output of the flip-flop is 
the NRZ-L representation of the data contained within 
the input signal. The remainder of the circuit is used to 
generate a clock to go with the NRZ-L data and then to 
BRIEF DESCRIPTION OF THE DRAWINGS 
FIG. 1 is a block diagram of the invention in which 
the carrier of the PSK input signal is 2Ntimes the bit 
FIG. 2 is the wave forms for the embodiment of the 
invention shown in FIG. 1 in which the carrier is four 
(22) times the bit rate. 
convert the NRZ-L data to Bi4-L data. 60 
rate; and 65 
2 
DETAILED DESCRiPTION OF THE 
INVENTION 
Turning now to the embodiment of the invention 
selected for illustration in the drawings, the numbers 11 
and 12 designate one-shot multivibrators which receive 
the PSK input signal. Multivibrator 11 is triggered on 
the rising edges and multivibrator 12 is triggered on the 
falling edges of the PSK input signal. The output pulse 
widths of multivibrators 11 and 12 are set to three- 
fourths of the expected carrier period of the PSK input 
signal. The inverted normal outputs Q of multivibrators 
11 and 12 are connected to the resets R of multivibra- 
tors 12 and 11, respectively. With this cross-coupling 
between the two multivibrators, if an input transition 
causes either multivibrator to pulse, a transition one-half 
period later is ignored. For a “one-zero” or “zero-one” 
bit pattern there is no transition at the data bit edge. 
This allows enough time (a whole period) to pass so that 
the pulsing mdtivibrator output can return to normal. 
The next transition is a function of the data bit value. 
Thus, by detecting which one-shot is pulsed, the value 
ofthe data bit is determined. The mdtivibrator outputs, 
Q1 and Qo, are connected to the set and reset inputs, 
respectively, of a flip-flop 13 for this purpose. The out- 
put of flip-flop 13 is the NRZ-L representation of the 
data contained within the input signal. This process 
results in a one-half carrier period delay in the formula- 
tiun of the NRZ-L signal. The demodulator should 
theoretically tolerate up to +25% jitter or frequency 
variation in the carrier before the multivibrators make 
incorrect indications. Any jitter or frequency variation 
in the carrier will be reflected to some degree in the 
demodulator output. 
To generate the clock to go With the NRZ-L data, a 
binary counter 17 is used. The modulus of the counter is 
seefected to be the number 2N of d e r  cycles within a 
PCM bit period. This use of a binary counter requires 
the carrier to be a 2Nmdtiple of the bit rate. If NRZ-L 
is ittf that is required from the demoduiator, the 2N 
restriction can be removed. The mdtivibrator outputs 
Qo and Q1 are “OR’ed together by a gate 14 to produce 
the dock CCK for the counter. This clock period is the 
same as that of the carrier. Since the counter performs 
a divide by 2N function, the Nth output QN of the 
counter is the bit rate clock BTCK. In order to synchro- 
nize the counter (bite rate clock) to the NRZ-L bit 
edges, a reset pulse (RST) is generated at every “one- 
zero” bit transition. A flip-flop 15 is used to create an 
NRZ-L signal delayed by the one-shot p u k  width. 
This delayed NRZ-L signal QA is “ A N D e d  with the 
inverse of NRZ-L by a gate 16 to provide the reset 
pulse RST for counter 17. 
To convert the NRZ-L and bit rate clock BTCK to 
Bi+-L data, “AND’ gates 18 and 20, an inverter 19 and 
an “OR” gate 21 are used. The bit clock BTCK and the 
inverted NRZ-L are applied to gate 18 and the BTCK 
is inverted by inverter 19 and then applied to gate u) 
along with the NRZ-L. The outputs of gates 18 and 20 
are applied to “OR” gate 21 which produces Bi+-L* 
data. Since this technique may create glitches at the bit 
edges, a flip-flop 22 is included prior to output. The 
QN-1 output stage of counter 17 is used to clock flip-flop 
22. This produces an additional one-fourth bit delay in 
the degtitched Bi+L output. 
Referring to FIG. 2 there is shown the wave forms 
for the embodiment of the invention in FIG. 1, where 
the carrier is four (22) times the bit rate. As is shown at 
4,3 1 3,103 
3 4 
the top of FIG. 2, the data that is transmitted for pur- outputs of said first and second one-shot multivibrators 
poses of illustration is the binary number 0110. The for generating said bit clock signals. 
period for the PSK carrier that is supplied to the two 3. A digital demodulator according to claim 2 
multivibrators is T and it requires four cycles of the wherein said means for generating said bit clock signals 
carrier to transmit one bit of binary information. The 5 comprises: 
output QO of multivibrator 11 is a series of four pulses a binary counter; 
each having a duration t = jT while the binary bit “0” is an OR gate connected to receive the normal outputs 
being transmitted; and the output Q1 of multivibrator 12 from said first and second one-shot multivibrators; 
is a series of four pulses while the binary bit “1” is being a second flip-flop with its data input connected to the 
transmitted. These outputs QO and Q1 are “0R”ed 10 normal output of said first flip-flop and with its 
together to form the CCK clock pulses. These outputs clock input connected to the output of said OR 
Q O  and Q1 of the multivibrators are also applied to the gate; 
reset and set inputs, respectively, of flip-flop 13 to pro- an AND gate with its inputs connected to the normal 
duce the NRZ-L data. The NRZ-L data is applied to output of said second flip-flop and to the inverted 
the flip-flop 15 to produce the QA data which is the I5 output of said first flip-flop; and 
NRZ-L data delayed by one of the CCK pulses. The a counter with its input connected to the output of 
inverted NRZ-L data is “AND”ed with the QA data to said OR gate and with its reset connected to the 
produce the RST signal. The CCK clock pulses and the output of said AND gate whereby the output of the 
reset pulses from the “AND” gate 16 are applied to the Nth stage of said counter is said bit clock signals. 
binary counter 17 to produce the BTCK clock pulses at 20 4. A digital demodulator according to claim 3 
the Nth stage of the counter. The NRZ-L data and the wherein said means for generating Bi4-L signals in- 
BTCK pulses are combined with the remaining logic cludes: 
circuitry to produce the Bi+-L data. It is noted that this a second AND gate with its inputs connected to the 
Bi4-L data carries the same binary information, 01 10, inverted output of said first flip-flop and to the 
with it that is carried by the PSK input data. output of the Nth stage of said counter; 
The advantages of this invention are that it is a sim- an inverter for inverting the output of the Nth stage 
ple, inexpensive demodulator circuit, that can be con- of said counter; 
structed using standard digital integrated circuits, for a third AND gate with its inputs connected to the 
converting PCM data from PSK to NRZ-L or Bi+-L . normal output of said first flip-flop and the inverted 
output of the Nth stage of said counter; and 
the spirit or scope of the invention. For example, differ- a second OR gate with its two inputs connected to 
ent carrier and bit rates can be accommodated by the outputs of said second and third AND gates 
changing the component values within the demodula- whereby the output of said second OR gate is the 
tor. A +20% jitter or frequency variation in the carrier Bi+-L signals. 
can be tolerated before the demodulator loses synchro- 35 5. A digital demodulator according to claim 4 
nization. The invention is disclosed as being built for wherein said meacs for generating Bi+-L signals further 
handling digital inputs but it could be used for sinusoi- includes: 
dal inputs with the inclusion of a waveshaping circuit a third flip-flop with its data input connected to the 
at the input. output of said second OR gate and with its clock 
What is claimed as new and desired to be secured by 40 input connected to the output of the (N-1) the stage 
Letters Patent of the United States is: of said counter whereby the normal output of said 
1. A digital demodulator for converting PCM data third flip-flop is the Bi4-L signals. 
from a 2N bit rate carrier PSK signal to Bi4-L compris- 6. A digital demodulator for converting PCM data 
ing: from PSK signals to NRZ-L signals and bit clock sig- 
means receiving the PSK signals for generating 45 nals comprising: 
NRZ-L data signals and bit clock signals; and a first one-shot multivibrator that is activated on the 
means responsive to said NRZ-L signals and said bit leading edges of pulses applied to it, connected to 
clock signals for generating Bi4-L signals at a bit receive said PSK signals; 
rate 1/2N times the PSK rate; a second one-shot multivibrator that is activated on 
wherein said means for generating said NRZ-L data 50 the following edges of pulses applied to it, con- 
signals comprises: nected to receive said PSK signals; 
a first one-shot multivibrator that is activated on the the inverted outputs of said first and second one-shot 
leading edges of pulses applied to it, connected to multivibrators connected to the reset inputs of the 
receive said PSK signals; second and first one-shot multivibrators, respec- 
a second one-shot multivibrator, that is activated on 55 tively; 
the following edges of pulses applied to it, con- a flip-flop having its reset and set inputs connected to 
nected to receive said PSK signals; the normal outputs of said first and second one-shot 
a flip-flop having its reset input connected to the multivibrators, respectively; whereby the normal 
normal output of said first one-shot multivibrator output of said flip-flop is the NRZ-L signals; and 
and having its set input connected to the normal 60 means connected to the outputs of said first and sec- 
output of said second one-shot multivibrators; and ond one-shot multivibrator and said flip-flop for 
the inverted outputs of said first and second one-shot generating said bit clock signals. 
multivibrators connected to the reset input of the 7. A digital demodulator according to claim 6 
second and first one-shot multivibrators, respec- wherein said means for generating said bit clock signals 
tively, whereby the normal output of the flip-flop is 65 comprise: 
said NRZ-L data signals. an OR gate with its inputs connected to the normal 
2. A digital demodulator according to claim 1 outputs of said first and second one-shot multivi- 
25 
Various changes can be made without departing from 30 
wherein means are connected to receive the normal brators; 
4,3 13,103 
a second flip-flop with its data input connected ti2 the 
normal output of the first flip-flop and with its 
clock input connected to the output of said OR 
gate; 
output of said second flip-flop and to the inverted 
output of the first flip-flop; and 
a counter with its inputs connected to the outputs of 
said AND and OR gates whereby the output of the 
Nth stage of said counter is said bit d o c k  signals. 5 
an AND gate with its inputs connected to the normal * * * * *  
20 
25 
30 
35 
45 
50 
55 
65 


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