A method is provided for making a high voltage multijunction solar cell. The cell comprises a plurality of discrete voltage generating regions, or unit cells, which are formed in a single semiconductor wafer and are connected together so that the voltages of the individual cells are additive. The unit cells comprise doped regions of opposite conductivity types separated by a gap. The method includes forming V-shaped grooves in the wafer and thereafter orienting the wafer so that ions of one conductivity type can be implanted in one face of the groove while the other face is shielded. A metallization layer is applied and selectively etched away to provide connections between the unit cells

Chai, A. T.

Evans, J. C., Jr.

Goradia, C. P.

English

NASA Technical Reports Server

United States Patent [191 
Evans. Jr. et al. 
[ I  11 4,335,503 
[45] Jun. 22, 1982 
[54] 
[75] Inventors: John C. Evans, Jr., Ravenna; An-Ti 
METHOD OF MAKING A HIGH VOLTAGE 
V-GROOVE SOLAR CELL 
Chai, N. Ridgeville; Chandra P. 
Goradia, Cleveland, all of Ohio 
[73] Assignee: The United States of America as 
represented by the Administrator of 
the National Aeronautics and Space 
Administration, Washington, D.C. 
[21] Appl. No.: 219,678 
[22] Filed: Dec. 24, 1980 
[51] Int. C1.3 ............................................. HOlL 31/18 
[52] US. C1. ...................................... 29/572; 136/249; 
148/1.5; 357/30 
[58] Field of Search ......................... 29/572, 589, 591; 
148/1.5; 136/249 MS; 357/30 
[561 References Cited 
U.S. PATENT DOCUMENTS 
4,200,472 4/1980 Chappell et al. .................... 136/246 
FOREIGN PATENT DOCUMENTS 
55-3660 1/1980 Japan .......................... 136/249 MS 
Primary Examiner-Aaron Weisstuch 
Attorney, Agent, or Firm-Norman T. Musial; John R. 
Manning; Gene E. Shook 
ABSTRACT [571 
A method is provided for making a high voltage multi- 
junction solar cell which comprises a plurality of dis- 
crete voltage generating regions, or unit cells, which 
are formed in a single semiconductor wafer (10) and are 
connected together so that the voltages of the individ- 
ual cells are additive. The unit cells comprise doped 
regions of opposite conductivity types (30, 32) sepa- 
rated by a gap. The method includes forming V-shaped 
grooves (16) in the wafer and thereafter orienting the 
wafer so that ions of one conductivity type can be im- 
planted in one face (e+, 16a) of the groove while the 
other face (e.g., 16b) is shielded. A metallization layer 
(22) is applied and selectively etched away to provide 
connections between the unit cells. 
7 Claims, 9 Drawing Figures 
I t  
P+ION FLUX 
n+lON FLUX 
https://ntrs.nasa.gov/search.jsp?R=19820021833 2020-03-21T17:14:13+00:00Z
U.S. Patent Jun. 22, 1982 Sheet 1 of 2 4,335,503 
I I  1 1  
I I I ” I 1 
12 
y 8  
p+ION FLUX 
r l  
n+lON FLUX 
F/G 
I I ,  I I1 
I I  I 
12 
F/G: /fg/ 
U.S. Patent Jun. 22, 1982 Sheet 2 of 2 4,335,503 
n+ COLLECTOR B 
FIG 3 
I '34' 
38 
4,335,503 
1 2 
being oriented during this step so that the first faces are 
protected and thus no ions of the opposite conductivity 
type are implanted therein. Thereafter metallization is 
provided in the grooves over the doped regions so as to 
5 connect the doped regions together. The metallization 
adjacent unit cells of which the two doped regions of 
the groove individually form part, a unit cell being 
formed by one doped region of one groove and an op- 
10 positely doped region of a second, adjacent groove and 
the two regions being separated by a gap therebetween. 
This gap can comprise an undiffused portion of the 
semiconductor body between the two grooves which 
separates the two regions. 
The grooves are preferably V-shaped and in a spe- 
cific exemplary embodiment, the angle between the 
In our concurrently filed copending application Ser. faces of a groove is 90” and the body is oriented at 45” 
No. 219,677, which is entitled “Planar Multijunction and 135”, respectively, during the two implantation 
Solar Cells”, and the subject matter of which is hereby steps. 
incorporated by reference, there is disclosed a new type 2o The metallization is preferably applied as a layer 
of solar cell exhibiting a high output voltage. In brief, which covers one entire surface of the semiconductor 
the solar cell in question comprises a multiplicity of body and selected portions of the layer are removed 
voltage generating regions within a single semiconduc- thereafter to provide the metallization between the 
tor wafer, each of the regions forming a unit cell within grooves as well as contacts or terminals at the edges of 
series so that the contributions of all of the cells are circuit. A photoresist masking step followed by an etch- 
abovementioned application is obviously not limited to as well as removing the unwanted portions of the metal- 
the planar multijunction cell disclosed in that applica- 30 coated with a metal oxide layer and all or substantially 
regions in a flat surface of the planar wafer by implanta- 
tion or diffusion of active and passive materials to form 
p+, metal, and n+ regions within the flat surface. The 
method of the present invention eliminates such im- 
planting of metal and thus offers substantial advantages 
as compared with the technique discussed above. 
METHOD OF MAKING A HIGH VOLTAGE 
V-GROOVE SOLAR CELL 
ORIGIN OF THE INVENTION 
ees of the US.  Government and may be manufactured 
and used by or for the Government for governmental 
purposes without the payment of any royalties thereon 
or therefor. 
TECHNICAL FIELD 
The invention described herein was made by employ- in an individual groove serves to connect together two 
The present invention relates to an improved method 
for making a high voltage solar cell. 
l5 
BACKGROUNDART 
the wafer and the being connected together in 25 the cell to enable the cell to be connected to an external 
added together. Although the solar cell disclosed in the 
such a method* a specific method for making 
ing step is preferably used both in forming the grooves 
lization layer. The semiconductor body is preferably 
provides for the Of the generating all of this layer is also removed with the removal of the 
unwanted metal. 
Other features and advantages of the invention will 
implanting of metal creates certain problems and the 35 be set forth in, Or apparent from, the descrip- 
tion of the preferred embodiments which follows. 
BRIEF DESCRIPTION OF THE DRAWINGS 
Reference is made to the patents and other materials FIGS. l(a) to illustrates sequential steps utilized 
cited in the abovementioned application for a discussion 40 in carrying out a preferred embdiment of the method 
of other prior art techniques of possible interest. of the invention; 
FIG. 2 is a perspective view of solar cell device con- 
structed in accordance with the method of the inven- 
tion; and 
FIG. 3 is an end view, Partially broken away, of a 
further embodiment of a solar cell constructed in accor- 
dance with the method of the i ~ e n t i o n .  
SUMMARY OF THE INVENTION * 
In accordance with the invention, a method is pro- 
vided for making a high voltage multijunction solar cell 45 
of the type discussed above, i.e., a solar cell wherein a 
plurality of discrete voltage generating regions or unit 
DETAILED DESCRIPTION cells are formed within a single semiconductor body or 
wafer and are connected together so the voltage out- 
puts of the individual unit cells are additive. As noted 50 to lot there is illustrated the 
hereinbefore, the method of the invention eliminates basic steps of forming the high voltage V-groove P-i-n 
metal implantation into the semiconductor body and solar cell of the invention. It will be appreciated that 
thus possesses significant advantages Over fabrication while a basic nine step process will be described, varia- 
methods which require such metal implantation. tions and modifications can be effected in these steps 
are formed in the surface of a semiconductor body, the In the first step, referring to FIG. l(a), a semiconduc- 
grooves having first and second faces arranged at an tor wafer 10, such as a single crystal of silicon, is ther- 
angle to one another. An ion flux is used to implant ions mally oxidized or otherwise coated with a dielectric or 
of a first conductivity type into the first faces of the insulating protective layer denoted 12. In an exemplary 
grooves so as to form doped regions of this first conduc- 60 embodiment, wafer 10 has a thickness of about one 
tivity type therein while the semiconductor body is’ hundred micrometers or 4 mils. 
oriented such that substantially none of the ions are In the second step, which is partially illustrated in 
implanted into the second faces of the grooves. In other FIG. l(b), the wafer is coated on one surface with a 
words, doped regions of a first conductivity type, e.g, photoresist material indicated generally at 14, the mate- 
n+ or p+, are selectively implanted in one face of the 65 rial 14 is exposed through a pattern mask to ultraviolet 
grooves. In the next step, doped regions of the opposite light, the exposed pattern is developed and the unpo- 
conductivity type are selectively formed in the second lymerized photoresist material is dissolved away, leav- 
or other faces of the grooves, the semiconductor body ing parallel strip-like regions of photoresist material, 
Referring to FIGS. 
According to the method of the invention, grooves 55 within the scope and spirit of the i ~ e n t i o n .  
4335,503 
3 
denoted 14u, on the surface of wafer to enable con- 
trolled silicon etching in the unprotected areas denoted 
1.46. 
In the third step, illustrated in FIG. I@), V-shaped 
grooves 16 are etched in tbe unprotected areas 14b 
through the oxide layer 12 into the silicon wafer 10. In 
specific exemplary embodiment, the etching gap, ie., 
the width of areas 34b, is approximately 70 micrometers 
wide and the depth of the etch is approximately ten 
micrometers from the oxide surface 12. The faces J6a 
and 165, of each groove 16 form an angle of approxi- 
mately 90" and the spacing between grooves 16 is ap- 
proximately 25 micrometers or 1 nil. Standard silicon 
etchants such as mixtures of hydrofluoric, nitric and 
acetic acids may be used in carrying out the etcfning step 
in accordance with conventional practice. 
In step four, illustrated in FIG. I@, pf- ions, e-g., 
boron ions, are implanted along one w d  01 face of each 
W-groove 16 by appropriately or ienhg the surface of 
the silicon wafer 10 in relation to the direction of the 
incident ions. As illustrated, the wafer 10 is oriented at 
an angle of about 45" so that the lines of p+ ion flux, 
indicated at 18, are approximately perpendicular to one 
set of the faces of the V-grooves, viz., faces 1 6 ~  The 
opposite walls or faces 16b of grooves 15 lie parallel to 
the direction of the ion beams 18 and thus the p+ ions 
are not incident upon these surfaces. 
In the fifth step, illustrated in FIG- l@), the wafer 10 
is again oriented at 45" but at an angle of 90" to the 
position for the fourth step. In fhis position, the other 
faces or walls 16b of grooves 16 are implanted with n+ 
ions, e.g., phosphorous ions. In this step, the faces 16b 
which receive the n+ ions are perpendicular to the n+ 
ion beam, indicated at 20, and the p+ doped faces M u  
lie pardel to the beam and hence are shielded. 
In the sixth step, the entire grooved wafer surface is 
coated with a metal layer 22, as illustrated in FIG. l(13. 
In a specific embodiment this surface is coated with 
vacuum deposited or sputtered aluminum to a thickness 
of several micrometers. 
In the seventh step, which is also illustrated in FIG. 
10, photoresist material, generally denoted 24, is selec- 
tively applied in the grooves and over the ends of tbe 
wafer face. The photoresist material is dried, exposed 
through a suitable mask, and developed and thereafter 
the unpolymerized material is removed to leave protec- 
tive strips 24u over the metallization layer 22 and pro- 
tective strips 24b at the opposite edges of wafer 20. 
In the eighth step, illustrated in FIG. 10, the areas 
which are not protected by strips 24.4 24b are etched so 
as to remove all of the underlying metallization layer 22 
and to remove the underlying oxide layer 12 to a depth 
closely approaching the silicon of wafer 10. Stated dif- 
ferently, a portion of the oxide layer 12 may be retained 
(and this hak advantages) but all of the metal must be 
removed to prevent shorting out of the unit voltage- 
generating regions. The resist plastic strips 24a, 24b are 
then removed. 
In the ninth and final step, the outermost grooves and 
connection tabs are *'tinned" wish solder to provide 
terminals for connection to the external circuit 
Referring to FIG. 2, a perspective view of the fin- 
ished solar cell is shown, a portion of the d l  bebg cut 
away to show details of the V-shave groove. As am- 
5 
10 
15 
20 
25 
30 
35 
40 
45 
4 
step are denoted 34 and provide a series connection 
between the p+ and n+ doped regions 3Q, 32. The 
"tinned*' metal tabs or terminals are indicated at 36. 
Referring to FIG. 3, there is shown a detail of a por- 
tion of a farther embodiment of a solar cell constructed 
which is generally in accordance With the method set 
forth above but which is modified with respect to the 
n+ collector region. The embodiment of FIG. 3 is 
similar to that shown in FIG. 2 and like elements have 
been given the same reference numerals, with primes 
attached. A unit cell or voltage generating region is 
formed by a pair of doped regions 30 and 32' separated 
by a gap region 38 of unimplanted semiconductor mate- 
&. The p+ region 32' of one unit cell is connected to 
d e  n+ region 30' of an adjacent cell by metallization 
34'. In the embodiment of FIG. 3, in contrast to that of 
FIG. 2, the n+ collector region 30' extends dong a 
substantial portion of the sudace of wafer 10'. In a pre- 
ferred embodiment, an approximate ratio of 1 to 8 is 
provided for the length of the p+ doped base region 
32' of groove 16 relative to the length of the n+ doped 
couector regon 30'. The length of the gap region 38 is 
about 25 micrometers in an exemplary embodiment 
where the bulk doping is ptype silicon, although it will 
be appreciated that, as provided for in the concurrently 
filed copendig application referred to above, other 
semiconductors, and other dimensions, can obviously 
be used. 
Although the invention has been described in relation 
to exemplary embodiments thereof, it will be under- 
stood by those sId3ed in the art that variations and 
modifications can be effected in these exemplary em- 
bodiments without departing from the scope and spirit 
of the invention. 
We claim: 
1. A method of making a solar cell of the type com- 
prising a plurality of discreet voltage generating Kegions 
formed witbin a single semiconductor body of one con- 
ductivity type having oppositely disposed surfaces said 
voltage generating regions being connected logether so 
that their output voltages are additive; said method 
comprising: 
forming a plurality of V-shaped grooves in one of 
said slufaces of said semiconductor body, each of 
said grooves being short of and spaced from the 
oppositely disposed surface and including first and 
second faces arranged in an angle ofnabout 90" to 
one another: 
59 orienting said iemiconductor body to a first position 
wherein said second faces are substantidy parallel 
to a &st ion flux thereby implanting ions of a first 
conductivity type into the said first faces of said 
grooves so as to f o m  a doped segion of said first 
conductivity type therein while said body is ori- 
ented in said f i s t  position so that substantially none 
of said ions from said first ion flux are implanted in 
said second faces of said groove; and 
orienting said semiconductor body to a second posi- 
tion wherein said first faces are substantially paraf- 
le1 to a second ion 47ux thereby implanting ions of 
an opposite conductivity type into the said second 
faces of said grooves so as to form a doped region 
of the Q P P O S ~ ~  conductivity type therein with said 
55 
60 
tratid, p+ regions 30 are formed ii one face of each of 65 
the grooves 16 whiie n+ regions 32 are formed to the 
other face of each groove. The portions of metallization 
body o6;nted in said second $osition so that sub- 
stantially none of said ions from said second ion 
flux are implanted in the said first faces of said 
grooves; layer 22 remaining in the grooves 16 after the etchig 
4,335,503 
5 6 
pairs of oppositely disposed doped regions of adja- 
cent grooves in said semiconductor body being 
spaced apart by gaps comprising unimplanted re- 
the adjacent grooves, said pairs of oppositely 
doped regions forming voltage generating unit 
cells and said method further comprising providing 
metallization in said grooves to connect together 
adjacent ones of said unit cells. 
in claim 1 wherein said semi- 
conductor body is oriented at 450 and 1350 to said ion 
flux during said ion implanting steps. 
grooves are formed using a photoresist masking step 
wherein the locations of said grooves on said planar 
surface are exposed for etching to produce said metal in the area of said unprotected portions. 
grooves. 
4. A method as claimed in claim 1 wherein said metal- 
lization is applied as a layer of metallization over the 
surface of said semiconductor body and portions of the 
layer removed thereafter to provide said metallization 
the body. 
5. A method as claimed in claim 4 wherein said por- 
tions of said layer are removed using a photoresist 
masking step and an etching step. 
6. A method as claimed in claim 1 wherein said semi- 
conductor body is initially covered with an oxide. 
7. A method as claimed in claim 6 wherein said metal- 
lization is applied as a layer, unprotected portions of 
said layer being removed thereafter using an etching 
wherein said 15 step while protected portions are left to form said metal- 
lization in said grooves, said etching step removing at 
least a major portion of said oxide layer and all of the 
gions Of semiconductor located between 5 in said grooves and to provide terminals at the edges of 
10 
2. A method as 
3. A method as ‘Iaimed in ‘Iaim 
* * * * *  
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Method of making a high voltage V-groove solar cell

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