A method of making V-MOS field effect transistors is disclosed wherein a masking layer is first formed over a surface of a crystalline substrate. An aperture is then formed in the masking layer to expose the surface of the substrate. An anisotropic etchant is applied to the exposed surface so that a groove having a decreasing width within increasing depth is formed. However, the etch is not allowed to go to completion with the result that a partially formed V-shaped groove is formed. Ions are accelerated through the aperture for implantation in the crystalline substrate in the lower portion of the partially formed V-shaped groove. Thereafter, an anisotropic etchant is reapplied to the partially formed V-shaped groove, and the etch is allowed to go to completion

Jhabvala, M. D.

English

NASA Technical Reports Server

United States Patent [191 
Jhabvala 
[111 4,272,382 
WI Jun. 9, 1981 
[54] METHOD OF MAKING V-MOS FIELD 
TWO-STEP ANISOTROPIC ETCHING AND 
EFFECT TRANSISTORS UTILIZING A 
ION IMPLANTATION 
[75] Inventor: Murzban D. Jhabvala, Seabrook, Md. 
[73] Assignee: The United States of America as 
represented by the Administrator of 
the National Aeronautics and Space 
Administration, Washington, D.C. 
[21] Appl. NO.: 72,727 
[22] Filed: Sep. 5, 1979 
[51] Int. C l . 3  ................... HOlL 21/265; HOlL 21/306 
[52] U.S. Cl. ....................................... 148A.5; 29/571; 
[58] Field of Search ................... 148A.5, 187; 29/571, 
29/578; 29/580; 148/187; 156/647; 156/648; 
156/649; 357/23; 357/55; 357/60; 357/91 
29/578,580; 156/647,648,649; 357/23,55,60, 
91 
r561 References Cited 
U.S. PATENT DOCUMENTS 
3,668,481 6/1972 Saltich et al. ...................... 357/55 X 
3,920,482 11/1975 Russell ............................... 357/55 X 
3,975,221 8/1976 Rodgers ............................. 29/571 X 
4,003,036 1/1977 Jenne ................................. 357/55 X 
4,003,126 VI977 Holmes et al. .................... 29/580 X 
4,049,476 9/1977 Horie ................................ 148/1.5 X 
4,056,413 11/1977 Yoshimura ......................... 29/580 X 
3,986,200 10/1976 Allison ................................... 357/55 
4,084,175 4/1978 Ouyang .................................. 357/55 
4,102,714 7/1978 DeBar et al. ......................... 148/187 
4,113,516 . 9/1978 Ponczak et al. ...................... 148/1.5 
4,116,720 9/1978 Vinson .................................. 148/1.5 
4,140,558 2/1979 Murphy et al. .................. 148/187 X 
4,156,289 5/1979 Hoffmann et al. ................ 357/55 X 
4,089,021 5/1978 Sato et al. ........................ 156/647 X 
Primary Examiner-L. Dewayne Rutledge 
Assistant Examiner-W. G. Saba 
Attorney, Agent, or Firm-John 10. Tresansky; John R. 
Manning; Robert D. Marchant 
[571 ABSTRACT 
A method of making V-MOS field effect transistors is 
disclosed wherein a masking layer is first formed over a 
surface of a crystalline substrate. An aperture is then 
formed in the masking layer to expose the surface of the 
substrate. An anisotropic etchant is applied to the ex- 
posed surface so that a groove having a decreasing 
width within increasing depth is formed. However, the 
etch is not allowed to go to completion with the result 
that a partially formed V-shaped groove is formed. Ions 
are accelerated through the aperture for implantation in 
the crystalline substrate in the lower portion of the 
partially formed V-shaped groove. Thereafter, an aniso- 
tropic etchant is reapplied to the partially formed V- 
shaped groove, and the etch is allowed to go to comple- 
tion. 
4 Claims, 11 Drawing Figures 
21, 23 24 In 22 20 
- 12 
II 
https://ntrs.nasa.gov/search.jsp?R=19810017823 2020-03-21T09:53:20+00:00Z
U.S. Patent 
FIG.1 
FI G. 2 
FIG.3 
FIG .4 
FIG.5 
FIG .6 
Jun. 9, 1981 Sheet 1 of 2 4,272,302 
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12 
II 
12 
I I  
U.S. Patent 
FIG.7 
FIG. 8 
FIG9 
Jun. 9, 1981 Sheet 2 of 2 4,272,302 
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FIG.10 II 
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FIG.11 I I  
4,272,302 m 1 
' METHOD OF MAKING V-MOS FIELD EFFECT 
TRANSISTORS UTILIZING A TWO-STEP 
ANISOTROPIC ETCHING AND ION 
IMPLANTATION 
ORIGIN O F  THE INVENTION 
The invention described herein was made by an em- 
ployee of the United States government and may be 
manufactured and used by or for the government for 
governmental purposes without the payment of any 
royalties thereon or therefor. 
BACKGROUND OF THE INVENTION 
The invention generally relates to the field of semi- 
conductor device manufacture and more particularly to 
a new method of making V-MOS field effect transistors. 
The basic advantage of V-MOS technology is the 
ability to provide a very short channel, L, between the 
source and drain regions of a field effect transistor with- 
out any deleterious effects. Prior art methods of manu- 
facturing V-MOS field effect transistors rely on the fact 
that anisotropic etchs are available that etch certain 
silicon crystal planes more readily than other crystal 
planes. N2H4 and ROH are two such etchants that dis- 
solve the <100> planes much more rapidly than the 
< 11 1 > planes. The channel length, L, of the V-MOS 
transistor can be easily calculated. < 11 1 > planes inter- 
sect the < 100> planes at 55 degrees. Knowing this, the 
channel length, L, is given by the following equation: 
L=2(0.86 W- 1 .X,), 
where W is the mask opening and X j  is the diffusion 
deDth. The channel length. L. is then controlled bv the 
5 
10 
15 
20  
25 
30 
35 
mask opening, W, and ;he diffusion depth, Xj, both of 
which can be only moderately controlled at best. Be- 
cause of this, diffusion spikes which short the source 
and drain regions of the transistor sometimes occur. A 
vast improvement in channel length control could be 40 
achieved if it were possible to eliminate the effect of 
either of the parameters W or Xj. 
SUMMARY OF THE INVENTION 
provide an improved method of making V-MOS field 
effect transistors wherein the parameter X, is eliminated 
as a controlling factor in determining the length of the 
channel in a V-MOS field effect transistor. 
precise control of the channel length in the manufacture 
of a V-MOS field effect transistor by a simple process. 
It is a further object of the invention to eliminate the 
effect of shorting diffusion spikes and the effects of 
furnace temperature variations, pre-deposition concen- 55 
tration and other factors determining final junction 
depth in the manufacture of V-MOS field effect transis- 
tors. 
The foregoing and other objects are accomplished by 
providing a method wherein a masking layer is first 60 
formed over a surface of a crystalline substrate. An 
aperture is then formed in the masking layer to expose 
the surface of the substrate. An anisotropic etchant is 
applied to the exposed surface so that a groove having 
a decreasing width with increasing depth is formed. 65 
However, the etch is not allowed to go to completion 
with the result that a partially formed V-shaped groove 
is formed. Ions are accelerated through the aperture for 
It is therefore an object of the present invention to 45 
It is another object of the invention to provide for the 50  
L 
implantation in the crystalline substrate in the lower 
portion of the partially formed V-shaped groove. 
Thereafter, an anisotropic etchant is reapplied to the 
partially formed V-shaped groove, and the etch is al- 
lowed to go to completion. By using ion implantation 
when the V-shaped groove is only partially formed and 
then completing the etch of the V-shaped groove, pene- 
tration of the ion implantation diffusion region between 
the source and drain regions is assured, and the resulting 
channel length can be very precisely controlled. 
BRIEF DESCRIPTION OF THE DRAWINGS 
The specific nature of the invention, as well as other 
objects, aspects, uses and advantages thereof, will 
clearly appear from the following description and from 
the accompanying drawings, in which: 
FIGS. 1 to 11 are cross-sectional views illustrating 
the process of manufacturing a V-MOS field effect 
transistor according to the present invention. 
DESCRIPTION OF THE PREFERRED 
EMBODIMENT 
Referring now to the drawings, the < 100> surface 
of an N- Si substrate 11 is oxidized in an 02, H20 
atmosphere at 1OOO" C. to form an Si02 layer 12 as 
shown in FIG. 1. The Si02 layer 12 is coated with a 
photoresist which is exposed, developed and rinsed to 
form a mask defining a P+ region aperture exposing 
Si02 layer 12. HF is applied to the exposed Si02 layer to 
expose the < 100> ,surface of the substrate 11 thereby 
forming the P+ region aperture 13 in the Si02 layer 12 
as shown in FIG. 2. Once this aperture is formed, the 
photoresist is removed with chromic acid and the wafer 
is rinsed. 
The exposed surface of the substrate 11 is predoped 
with boron. The predoped substrate is then heated in an 
oxygen atmosphere to diffuse B+ into the substrate 11 
to form the P+ region 14 as shown in FIG. 3. This 
region will be divided into source and drain regions as 
will become apparent from the following description. 
The diffusion process is well known to those skilled in 
the art and it is carried out for a time and at a tempera- 
ture to provide the desired diffusion depth of the P+ 
region. For example, the substrate can be heated for 10 
minutes in an 0 2  atmosphere at lOo0" C.  followed by 40 
minutes in an 02, H20 atmosphere at looo" C .  This can 
be followed by heating the substrate in a 0 2  atmosphere 
at 1200" C. for a short time to further increase the diffu- 
sion depth. Inherent in this diffusion process is the for- 
mation of an Si02 layer 15 over the P+ region as shown 
in FIG. 4. It is desirable to increase the thickness of this 
layer, and this is accomplished by heating for 50 min- 
utes in an 02, H20 atmosphere at looo" C. 
The Si02 layer is again coated with a photoresist 
which is exposed, developed and rinsed to form a V- 
groove mask exposing the Si02 layer. H F  is applied to 
the exposed Si02 layer to expose the < 100> surface of 
the substrate 11 to form a V-groove aperture 16 as 
shown in FIG. 5. The photoresist is then removed with 
chromic acid, and the wafer is rinsed. 
The next step is to apply the anisotropic etch KOH to 
the exposed < 100> surface of the substrate 11. Up to 
this point, the process described is quite conventional, 
and normally the anisotropic etch would etch a self- 
stopping V-groove in the substrate. According to the 
invention, however, instead of letting the etch go to 
completion, it is only allowed to go to partial comple- 
4,272,302 
3 4 
tion resulting in the structure shown in FIG. 6. This is 
accomplished by applying KOH at 80" C. for 10 min- 
Utes. The KOH etch is stopped by transferring the 
wafer to a water bath. It will be observed that the par- 
tially formed V-groove 17 penetrates the P+ region 14 5, claims. 
dividing it into two parts which will become the source 
and drain regions of the field effect transistor. 
Ion implantation is then carried out by accelerating 
boron ions at 52 Kev in a concentration of 1013B+ 
ions/cm2 through the aperture for implantation in the 10 
substrate 11 in the lower portion of the partially formed 
V-groove 17. The substrate is then heated for 15 min- 
utes in an N2 atmosphere at 1OOO" C. to produce the 
diffusion region 18 shown in FIG. 7. Ion implantation is 
a very accurate and precise method of defining the 15 
crucial geometry of the diffusion 18, and this is critical 
to the invention as will be appreciated as the description 
proceeds. 
The wafer may be dipped in H F  for approximately 10 
seconds and then rinsed. This has the effect of beveling 20 
the edge of the Si02 Layer. The KOH is reapplied to a 
period of approximately 6 minutes so that the V-groove 
etch is completed as shown in FIG. 8. As is now appar- 
ent from FIG. 8, the completed V-groove 17 com- 
pletely penetrates the diffusion region 18 thereby assur- 25 
ing that no shorts due to diffusion spikes will occur. The 
channel length, E, as produced by the process accord- 
ing to the invention is defined by the following expres- 
sion: pleted V-shaped groove. 
sistor comprising the steps of: 
It will be understood by those skilled in the art that 
the embodiment shown and described is only exemplary 
and that various modifications can be made in the prac- 
tice of the invention within the scope of the appended 
What is claimed is: 
1. A method of making a V-MOS field effect transis- 
forming a masking layer over a surface of a crystal- 
opening an aperture in said masking layer to expose 
applying an anisotropic etchant to said exposed sur- 
' face to etch a groove in said crystalline substrate, 
said groove having a decreasing width with in- 
creasing depth; 
inhibiting the effect of said anisotropic etchant before 
the etch goes to completion so that a V-shaped 
groove is only partially formed; 
accelerating ions through said aperture for implanta- 
tion in said crystalline substrate in the lower por- 
tion of the partially formed V-shaped groove; and 
thereafter reapplying an anisotropic etchant to said 
partially formed V-shaped groove and allowing 
the etch to go to ComPletion- 
2. The method of making a V-MOS field effect Wan- 
SiStOr as recited in Claim 1 further including the step Of: 
forming an oxide layer on the surfaces of the com- 
3. The method of making a V-MOS field effect tran- 
tor comprising the steps of: 
line substrate; 
said surface of said substrate; 
3 0  
L'=2(0.86)W, 
where W' is now determined by W and the etchant 
time. The ion implantation defines the bottom ledge of 
the diffusion insuring uniformity. The channel length, 35 
L', is independent of furnace time provided high tem- 
perature is avoided to keep the diffusion relatively shal- 
low. 
T o  complete the manufacture of the V-MOS field 
effect transistor, chromic acid is applied to the wafer, 40 
and the wafer is then rinsed. An oxide layer 19 is formed 
on the surfaces of the completed V-groove as shown in 
FIG. 9 by heating in an atmosphere of 0 2 ,  H20 for 30 
minutes at looo" C. The oxide layer 19 will form the 
gate oxide and may be further treated to increase its 45 
thickness or vary its electrical properties according to 
processes which are well known in the art. The result- 
ing Si02 layer is then coated with a photoresist which is 
exposed, developed and rinsed to form a mask defining 
source and drain electrode regions on either side of the 5 0  
V-groove exposing the Si02 layer. H F  is applied to the 
exposed Si02 layer to expose the surface of the substrate 
11 forming apertures 20 and 21 as shown in FIG. 10. 
Thereafter, the photoresist is removed with chromic 
acid, and the wafer is rinsed. Metallic electrodes are 55 
then deposited on the exposed source and drain elec- 
trode regions and on the gate oxide layer to form 
source, drain and gate electrodes 22,23 and 24, respec- 
tively, as shown in FIG. 11. 
vention can be summarized as follows: 
The advantages of the process according to the in- 60 
1. The effect of shorting diffusion spikes is eliminated. 
2. The very accurate and precise method of ion im- 
plantation defines the crucial geometry of the diffusion. 
3. The effect of furnace temperature variations, 65 
predeposition concentration and other factors determin- 
ing final junction depth is eliminated. 
forming-a masking layer over a surface of a crystal- 
line substrate of one conductivity type; 
opening a first aperture in said masking layer to ex- 
pose said surface of said substrate; 
forming a region of a second conductivity type in said 
substrate through said first aperture; 
forming an oxide layer over the exposed surface of 
said substrate to cover said region of said second 
conductivity type; 
thereafter opening a second aperture in said oxide 
layer to expose a surface over said region of said 
second conductivity type, said second aperture 
being smaller than said fust aperture; 
applying an anisotropic etchant to said exposed sur- 
face over said region of said second conductivity 
type to etch a groove in said crystalline substrate, 
said groove having a decreasing width with in- 
creasing depth; 
inhibiting the effect of said anisotropic etchant before 
the etch goes to completion so that a V-shaped 
groove is only partially formed, the partially 
formed V-shaped groove penetrating said region of 
said second conductivity type and dividing it into 
two parts; 
accelerating ions through said second aperture for 
implantation in said crystalline substrate in the 
lower portion of the partially formed V-shaped 
groove, said ions forming a bridging diffusion re- 
gion of said second conductivity type connecting 
the two parts of the region divided by said partially 
formed V-shaped groove; and 
thereafter reapplying an anisotropic etchant to said 
partially formed V-shaped groove and allowing 
the etch to go to completion, the completed V- 
shaped groove penetrating said bridging region. 
4. The method of making a V-MOS field effect tran- 
2. The-process is simple. sistor as recited in claim 3 further including the steps of: 
4,272,302 
5 6 
to expose surfaces over the divided parts of said 
region of said second conductivity type; and 
forming metallic electrodes con said exposed surfaces 
and on the oxide layer on the surfaces of the com- 
pleted V-shaped groove. 
forming an oxide layer on the surfaces of the com- 
pleted V-shaped groove; 
opening third and fourth apertures in said oxide layer 
on either side of said completed V-shaped groove * * * * *  
20 
25 
30 
35 
40 
45 
50 
55 
60 
65 


Method of making V-MOS field effect transistors utilizing a two-step anisotropic etching and ion implantation

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