A delay-locked loop is presented for tracking a pseudonoise (PN) reference code in an incoming communication signal. The loop is less sensitive to gain imbalances, which can otherwise introduce timing errors in the PN reference code formed by the loop

Laflame, D. T.

English

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NATIONAL AERONAUTICS AND SPACE ADMINISTRATION
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Bonnie L. Henderson
 S;'5 ^ "•./;'\
(NaSA-Case-MSC-18035-1) PSEUDONOISE CODE U81-15179
IfiACKING LOOP Patent (NASA) 5 p CSCL 17B
Unclas
00/32 40768
https://ntrs.nasa.gov/search.jsp?R=19810006664 2020-03-21T09:08:59+00:00Z
•/
United States Patent
La Flame [45]
4,221,005
Sep. 2, 1980
[54] PSEUDONOISE CODE TRACKING LOOP
[76] Inventor: Robert A. Frosch, Administrator of
the National Aeronautics and Space
Administration, with respect to an
invention of David T. La Flame, Los
Angeles, Calif.
[21] Appl. No.: 41,142
[22] Filed: May 21,1979
[51] Int. C1.3 H04K 1/04
[52] U.S. a 375/1; 375/115;
375/58
[58] Field of Search 325/32, 42, 65, 321,
325/323, 324, 419, 320; 329/50, 122; 178/69.1,
67, 88, 66 R; 340/146.1 D
[56] References Cited
U.S. PATENT DOCUMENTS
3,305,636 2/1967
4,039,749 8/1977
4,122,393 10/1978
Webb .................................. 178/69.1
Gordy et al ......................... 325/320
Gordy et al ......................... 325/324
Primary Examiner — Benedict V. Safourek
Attorney, Agent, or Firm— Russell E. Schlorff; John R.
Manning; Marvin F. Matthews
[57] ABSTRACT
A delay-locked loop is provided for tracking a pseudo-
noise (PN) reference code in an incoming communica-
tion signal. The loop is less sensitive to gain imbalances,
which can otherwise introduce tuning errors in the PN
reference code formed by the loop.
15 Claims, 2 Drawing Figures
LOOP ERROR
SIGNAL, 6(t)
f60 PN REFERENCE
L
 / CODE
Sep. 2, 1980 4,221,005
LOOP ERROR
SIGNAL,€"(»)
n - STAGE SHIFT REGISTER
PN REFERENCE
( CODE
} ^^ Q ( I \
FIG. I (PRIOR ART)
40
LOOP ERROR
SIGNAL, 6(t)
r56
n- STAGE SHIFT REGISTER
FIG.
s-60 PN REFERENCE
L
 1 / CODE
DELAY /
Tc/2
4,221,005
PSEUDONOISE CODE TRACKING LOOP
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to pseudonoise code
tracking loops.
2. Description of Prior Art
Various types of loops have been proposed for re-
ceivers to track an incoming signal. Some, such as in lo
U.S. Pat. Nos. 3,710,261; 3,806,815; 3,828,138; 3,943,468
and 4,027,265 have used phase-locked loops for tracking
purposes. Others, such as in U.S. Pat. Nos. 3,402,265
and 3,947,634 have formed a local pseudonoise se-
quence which was used for synchronization purposes. 15
Two other types of tracking loops were also known.
A first type, known as a delay-locked loop, was de-
scribed in an article "Noncoherent Pseudonoise Code
Tracking Performance of Spread Spectrum Receivers",
I.E.E.E. Transactions on Communications, Vol. com- 20
25, No. 3, March, 1977, at pages 327-345. These delay-
locked loops had two signal processing sections or arms
which were used to form a loop error signal for use in
tracking. In the event of gain imbalance in these two
arms, however, direct current offset or bias was caused 25
in the loop error signal, which resulted in a d.c. timing
error in the reference code formed by the loop.
A second type of tracking loop was known as a "tau-
dither" loop and was used as a tracking loop in place of
the delay locked loop to alleviate the gain imbalance 30
discussed above. However, although the tau-dither loop
apparently overcame gain imbalance problems, it did
not exhibit comparable tracking performance to the
delay locked loop. The performance differences of the
tau-dither loop could cause tracking problems in com- 35
munication systems where communication link margins
were critical or where link margin problems arose.
SUMMARY OF INVENTION
Briefly, the present invention provides a new and 40
improved tracking apparatus for forming a pseudonoise
reference code from an incoming signal. A pseudonoise
code is generated in the form of a multiple bit reference
code in response to an error signal. The error signal is
formed in a circuit receiving input product signals 45
formed in multiplier circuits. The multiplier circuits
form the product signals by multiplying the incoming
signal by sum and difference signals representing the
sum and the difference, respectively, of two selected
bits of the reference code. 50
With the tracking apparatus of the present invention,
gain levels in the arms affect only loop gain, so that the
gain imbalance problems of the prior art are overcome,
while also retaining performance advantages over the
prior art tau-dither loop. 55
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic electrical circuit diagram of a
prior art delay locked loop; and
Fig. 2 is a schematic electrical circuit diagram of a 60
pseudonoise tracking loop according to the present
invention.
DESCRIPTION OF PREFERRED EMBODIMENT
At the outset, a brief description of a prior art delay 65
lock loop D is submitted to be beneficial, in order to
more clearly understand the operation of the tracking
loop L (FIG. 2) of the present invention. In the prior art
delay lock loop D, an incoming signal in the form of a
received signal S(t) having therewith a noise compo-
nent N(t) is provided to signal processing arms 6 and 8,
which include multipliers or product forming circuits
10 and 12, respectively. The multiplier 10 receives a
second input signal Pn(t—Tc/2), often termed a late
reference code, formed in stage n of a shift register 14
which functions as part of a pseudonoise (PN) code
generator, where Tc represents the chip period or time
duration a digital bit is present in each stage of the shift
register 14 during travel therethrough. Similarly, the
multiplier 12 receives an input signal Pn(t+Tc/2),
known as an early reference code, from a stage n — 1 of
the shift register 14.
Each of the multipliers 10 and 12 forms a product
signal from the two input signals provided thereto
which are furnished to band pass filters 16 and 18, re-
spectively. The band pass filters 16 and 18 form filtered
output signals representing the product of the signal S(t)
and the input signals to multipliers 10 and 12, respec-
tively, which will hereinafter be referred to as A and B,
respectively, for purposes of brevity.
Signals A and B from the filters 16 and 18 are fur-
nished to square law devices 20 and 22 which form
output signals A2 and B2, respectively, from the pro-
cessing arms 6 and 8.
A summing function circuit 24 receives these signals
A2 and B2 and forms a loop error signal «(t) which is
represented by the difference between the input signals
A2 and B2. The loop error signal e(t) is furnished to a
loop filter 26 and therefrom to a voltage controlled
oscillator (VCO) 28 which forms signals which are
provided to the shift register 14 of the pseudonoise (PN)
code generator. Stage n—1 of the shift register 14 is
electrically connected to a delay circuit 30 with a time
delay Tc/2 so that the signal transferred from the shift
register 14 after such a time delay in the circuit 30 repre-
sents a pseudonoise reference code Pn(t) As has been
discussed above, a gain imbalance between the arm 6
and the arm 8 of the detector D caused an offset or bias
in the loop error signal t(t) which was transferred
through the loop filter 26 and oscillator 28 to the shift
register 14, in effect resulting in a direct current (DC)
timing error in the referenced pseudonoise code P«(t).
considering now a pseudonoise code tracking loop L
(FIG. 2) according to the present invention, the incom-
ing signal S(t)+N(t) is received at signal multiplier
circuits 40 and 42. The multiplier circuits 40 and 42
further receive a pseudonoise reference code from a
pseudonoise code generator including an n-stage shift
register 44. However, with the present invention, in
contrast to the prior art, a sum signal
Pn(t+Tc/2)+Pn(t-Tc/2) and a difference signal
Pn(t - Tc/2)—Pn(t+Tc/2) are formed in two summing
function circuits 46 and 48.
The summing function circuit 46 receive the contents
P«(t—Tc/2) from stage n of the shift register 44 at a first
positive input. Similarly, the summing function circuit
46 receives the contents Pn(t+Tc/2) of stage n—1 of
the shift register 44 at a second positive input. The
summing function circuit 46 thus forms the sum of the
two input signals as the output signal
Pn(t + Tc/2)+ Pn(t —Tc/2) which is furnished as a sec-
ond input to the multiplier circuit 40. The multiplier
circuit 40 thus forms a sum product signal by multiply-
ing the output of the summing function circuit 46 with
the incoming signal.
4,221,005
The summing function circuit 48 receives the con-
tents Pn(t— Tc/2) of stage n of the shift register 44 at a
positive input and the contents Pn(t+Tc/2) of the shift
register 44 at a negative input. The summing function
circuit 48 forms a difference signal as the sum of these 5
two input signals, or Pn(t— Tc/2)— Pn(t+ Tc/2), due to
receipt of one input signal at a negative input. The dif-
ference signal from circuit 48 is provided as an output
signal which is furnished to the multiplier circut 42. The
multiplier circuit 42 forms a difference product signal 10
by multiplying the difference signal output of the sum-
ming function circuit 48 with the incoming signal.
With the present invention, by forming the sum and
difference signals in the summing circuits 46 and 48, the
data content of both of the stages of the shift register 44 15
is present in the output sum and difference product
signals formed in the multipliers 40 and 42. Accord-
ingly, any gain imbalance between the multipliers 40
and 42 and their respective band pass filters 50 and 52
acts equally on the data content of both stages of the 20
shift register 44. Thus, in contrast to the prior art loop
D of FIG. 1, where a gain imbalance between the arms
6 and 8 affected only the data contents of one stage of
the shift register, the adverse effect of gain imbalance
on the loop error signal e(t) is avoided. 25
A band pass filter 50 receives and passes signal com-
ponents representing the product of the data portion
S(t) of the incoming signal and the sum signal from the
summing circuit 46. For convenience of reference, these
components are referred to as A+B hereinafter in the 30
drawings. Similarly, the output of the filter 52 includes
components representing the product of the data por-
tion S(t) of the incoming signal and the difference signal
furnished to multiplier 42 from the summer 48. In a
similar manner, these components for convenience of 35
reference are referred to in the drawings as A— B. The
output signals from the filters 50 and 52 are furnished to
a multiplier circuit 54 which forms a product of the two
signals furnished thereto which is furnished as a loop
error signal e(t) through a loop filter 56 and a voltage 40
controlled oscillator 58 to furnish output signal to the
shift register 44 in the pseudonoise code generator.
A time delay circuit with a time delay of Tc/2 is
electrically connected to stage n— 1 of the shift register
44 so that the data contents Pn(t+Tc/2) of such stage, 45
after the time delay of the time delay circuit 60, repre-
sents an output pseudonois reference code Pn(t) which
is formed in the loop L of the present invention.
From the foregoing, it can be seen that the loop L of
the present invention avoids the problems caused by 50
gain imbalance between two multipliers and filters pres-
ent in the prior art loop D. Additionally, with the loop
L, any imbalance in arm gain effects only the loop gain
of the loop L, since it applies equally to both digital
signals provided as output codes from the pseudonoise 55
code generator for tracking purposes.
Furthermore, the loop L has equivalent tracking
performance to the loop D. As has been set forth above,
the loop error signal e(t) formed in the loop D repre-
sents the difference between the outputs of the square 60
law devices 20 and 22, or, A2— B2. In the loop L, the
multiplier 54 receives the output signal A+B from the
filter 50 and the output signal A— B from the filter 52
and multiplies these two signals together. Accordingly,
the loop error signal e(t) formed in the multiplier 54 65
represents the product of the two input signals or
(A+B)X(A— B) or A2— B2, the identical loop error
signal formed in the prior art loop D. Accordingly, the
loop error signals are identical and the loops will thus
have identical tracking performance.
From the foregoing, it can be seen that a new and
unproved tracking loop is provided with the present
invention, overcoming problems of gain imbalance in
the prior art tracking loops without requiring the de-
creased tracking performance of tau-dither loops expe-
rienced in the past.
It should further be understoor that the summing
circuits 46 and 48 are shown as receiving two time
successive signals from the shift register 44 as the early
and late reference pseudonoise codes only by way of an
exemplary embodiment. Any other time spacing to
obtain early and late reference pseudonoise codes from
the shift register 44 could equally as well be made. For
example, for a shift register having n stages, where n is
a number greater than 2, connection could be made for
the late reference code to a stage n— y, where y is an
integer 2 or larger but less than n.
The foregoing disclosure and description of the in-
vention are illustrative and explanatory thereof, and
various changes in the size, shape, materials, compo-
nents, circuit elements, wiring connections and
contacts, as well as in the details of the illustrated cir-
cuitry and construction may be made without departing
from the spirit of the invention.
What is claimed is:
1. A tracking apparatus for forming a pseudonoise
reference code from an incoming signal, comprising:
(a) pseudonoise code generating means for forming a
multiple bit pseudonoise reference code in response
to a loop error signal;
(b) means for forming signals representing the sum
and the difference between two selected bits of the
pseudonoise reference code;
(c) first multiplier means for forming a first product
signal from the sum signal and the incoming signal;
(d) second multiplier means for forming a second
product signal from the difference signal and the
incoming signal;
(e) means for forming the loop error signal from the
first and second product signals to cause operation
of said pseudonoise code generating means.
2. The tracking apparatus of claim 1, wherein said
means for forming comprises:
summing function circuit means.
3. The tracking apparatus of claim 2, wherein said
summing function circuit means comprises:
(a) a first summing function circuit for forming the
sum of the two selected bits of the pseudonoise
reference code; and
(b) a second summing function circuit for forming the
difference between the two selected bits of the
pseudonoise reference code.
4. The tracking apparatus of claim 1, wherein said
pseudonoise code generating means comprises:
a multiple stage digital signal storage means.
5. The tracking apparatus of claim 4, wherein said
multiple stage digital storage means comprises:
a multiple stage shift register having n stages, wherein
n is a positive integer greater than one.
6. The tracking apparatus of claim 5, wherein said
means for forming comprises:
means for forming signals representing the sum and
the difference between the contents of stages n and
n— 1 of said shift register.
7. The tracking apparatus of claim 6, wherein said
means for forming comprises:
4,221,005
5 6
means for forming signals representing the sum and (d) forming a second product signal from the differ-
the difference between the contents of stages n and ence signal and the incoming signal;
n—y, wherein y is an integer greater than 1 but less (e) forming the loop error signal from the first and
than n. second product signals to cause said step of gener-
8. The tracking apparatus of claim 1, further includ- 5 ating.jng. 12. The tracking apparatus of claim 1, wherein said
(a) loop filter means for receiving the loop error step of forming signals representing the sum and differ-
signal and forming therefrom an output signal ence comPnses:
whose voltage varies in accordance with the error <a> forming the sum of the two selected bits of the
signal- and 10 pseudonoise reference code; and
(b) voltage controlled oscillator means. ^JfT? "* d|ference bfween th*two selected
9. The tracking apparatus of claim 1, further includ- *£,of the pseudono.se reference code.e
 ** 13. The method of claim 12, wherein the pseudonoise
ln% . ,.,, . . . „ . . . .. code is a sequence of n bits, n being a positive integer,band pass filter means electrically connected at the ,5 ^ ^ ^ of formi suffl J[ d£erence si *als
output of each of said first multiplier means and comprises-
said second multiplier means. forming signals representing the sum and the differ-
10. The tracking apparatus of claim 1, wherein said
 ence between the contents of stages n and n-1 of
means for forming the loop error signal comprises: ^^
 snjft regjster
means for multiplying the first and second products
 20 14 Tlle method oj claim 13> wherein said step of
signals together to form the loop error signal. forming comprises:
11. A method of forming a pseudonoise reference forming signals representing the sum and the differ-
code from an incoming signal, comprising:
 ence between the contrents of stages n and n-y,
(a) generating a multiple bit pseudonoise reference wherein y is an integer greater than 1 but less than
code in response to a loop error signal; 25 n.
(b) forming signals representing the sum and the dif- 15. The method of claim 11, wherein said step of
ference between two selected bits of the pseudo- forming the loop error signal comprises:
noise reference code; multiplying the first and second products signals to-
(c) forming a first product signal from the sum signal gether to form the loop error signal,
and the incoming signal; 30 * * * * *
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Pseudonoise code tracking loop

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