In a paralleled inverter system, a positive feedback current derived from the total current from all of the modules of the inverter system is applied to the base drive of each of the power transistors of all modules, thereby to provide all modules protection against open or short circuit faults occurring in any of the modules, and force equal current sharing among the modules during turn on of the power transistors

Nagano, S.

English

NASA Technical Reports Server

United States Patent [191 
Nagano 
[111 4,222,098 
PSI Sep. 9,1980 
[54] BASE DRIVE FOR PARALLELED INVERTER 
SYSTEMS 
[76] Inventor: Robert A. Frosch, Administrator of 
the National Aeronautics and Space 
Administration, with respect to an 
invention of Satoshi Nagmo, Long 
Beach, Calif. 
[21] Appl. No.: 878,541 
[22] Filed: Feb. 16, 1978 
[51] Int. (3 .2  ............................................. H02H 7/122 
[52] U.S. CI .  ........................................ 363/71; 363/56; 
363/78 
[58] Field of Search ....................... 363/25, 65, 71, 78, 
363/95, 97, 22, 23, 133, 134, 50, 56; 307/82 
[561 References Cited 
US. PATENT DOCUMENTS 
2,668,919 2/1954 Puchy ................................ 3071’82 X 
2,990,517 6/1961 Grieg ................................. 363/23 X 
3,549,977 12/1970 Watkins ................................. 363/71 
3,621,365 11/1971 Beck ....................................... 363/71 
3,675,037 7/1972 Hamilton ........................... 363/71 X 
3,832,622 8/1974 Compoly ................................ 363/72 
3,986,101 11/1976 Koetsch et al. ................... 307/82 X 
4,021,719 5/1977 Patel ....................................... 363/56 
Primary Examiner-J. D. Miller 
Assistant Examiner-Peter S. Wong 
Attorney, Agent, or Firm-Monte F. Mott; John R. 
Manning; Paul F. McCaul 
1571 ABSTRACT 
In a paralleled inverter system, a positive feedback 
current derived from the total current from all of the 
modules of the inverter system is applied to the base 
drive of each of the power transistors of all modules, 
thereby to provide all modules protection against open 
or short circuit faults occuring in any of the modules, 
and force more equal current sharing among the mod- 
ules during turn-on of the power transistors. 
5 Claims, 2 Drawing Figures 
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pair of transistors QA and QB, the power transistors Q B ~  
. . . Q ~ ~ a r e  then turned on at the same time during the 
alternate half cycle of a control clock signal. Now if the 
transistor Q B ~  starts to turn on faster than another corre- 
sponding transistor, such as transistor QBN, the output 
current of transistor Q B ~  is larger than that of transistor 
QBN because of transistor response difference. There- 
fore, transistor Q B ~  is accelerated to turn on further than 
during the slow turn on of transistor QBN. This results 
in high spike generation during turn-on of transistor 
QB~.  Such an effect might stress the faster switching 
transistor sufficiently to produce failure of that transis- 
tor. Moreover, such an individual output current feed- 
back arrangement can cause undesirable inverter system 
oscillation in the event of an open circuit in one of the 
two primary windings of the push-pull operated trans- 
formers TI employed to control base current in the 
power transistors. 
An object of this invention is to provide an arrange- 
ment for applying a composite feedback current derived 
from all of the modules of paralleled inverter modules 
to the base drive of each of the modules thereby to 
provide the entire system with protection against open 
or short circuit faults occuring in any of the modules. 
SUMMARY OF THE INVENTION 
In accordance with the present invention, an im- 
proved base drive arrangement is provided for power 
transistors in paralleled inverter modules connected to a 
common load comprising means for deriving substan- 
tially equal positive feedback currents for all modules 
from the common load current, means for combining 
said positive feedback currents with base drive currents 
for the power transistors of each of the modules, with 
the base drive current for normal operating conditions 
set only slightly higher than the derived feedback cur- 
rent so that, under overload conditions, the feedback 
current can affect control over the base drive current of 
the power transistors in each of the modules. This ar- 
rangement provides internal failure isolation while af- 
fecting overload protection for the entire inverter sys- 
tem and is easily achieved by a separate winding on 
each current pulse transformer coupling the clock input 
signal control to the base circuit of the power transistors 
and connecting each of those windings in series with the 
load. The arrangement also provides improved effi- 
ciency and better initial load sharing than in prior art 
circuits having no feedback control or having individ- 
ual output current feedback control. 
The novel features of the invention are set forth with 
particularity in the appended claims. The invention will 
best be understood from the following description when 
read in conjunction with the accompanying drawings. 
BRIEF DESCRIPTION OF THE DRAWINGS 
FIG. 1 illustrates in a circuit diagram the base drive 
circuit of a prior-art individual feedback arrangement. 
FIG. 2 illustrates in a circuit diagram the improved 
base drive circuit of the present invention. 
DESCRIPTION OF PREFERRED 
EMBODIMENTS 
Referring now to the drawings, the same reference 
numerals are employed for the circuit illustrating the 
prior-art feedback arrangement in FIG. 1 and the cir- 
cuit embodying the present invention in order to facili- 
tate understanding the difference between the prior art 
1 
BASE DRIVE FOR PARALLELED INVERTER 
SYSTEMS 
ORIGIN OF INVENTION 
The invention described herein was made in the per- 
formance of work under a NASA contract and is sub- 
ject to the provisions of Section 305 of the National 
Aeronautics and Space Act of 1958, Public Law 85-568 
(72 Stat. 435; 42 USC 2457). 
BACKGROUND OF THE INVENTION 
This invention relates to an inverter system having a 
plurality of modules connected in parallel to a load, and 
more particularly to an arrangement that applies a com- 
posite feedback current derived from all of the modules 
to the base drive of each of the modules, thereby to 
provide the entire system with protection against open 
or short circuit faults occuring in any of the modules. 
The type of circuit selected for driving the output 
power transistors of paralleled inverter modules has a 
large influence on system efficiency, redundancy capa- 
bility, load sharing and overload tolerance. In the past, 
there have been two base drive circuits customarily 
used for the power output transistors of paralleled mod- 
ules of the same push-pull type employed in the present 
invention, but in one the base drive circuit is without 
any current feedback from the load, and in the other 
shown in FIG. 1 the base drive circuit is with output 
current feedback from each individual module. Thus, in 
one prior-art type of circuit customarily used for driv- 
ing the output transistors of a multi-module, paralleled 
inverter system, no current feedback is provided for 
control, and in the other type of circuit customarily 
used, feedback in each module is limited to control of its 
own drive. 
Both prior-art arrangements have deficiencies. In the 
case of no feedback, the base current of push-pull power 
transistors is held constant regardless of the output load 
value. Therefore power dissipation in the base circuit is 
the same regardless of the load so that efficiency de- 
creases with lighter loads. In the case of individual 
output current feedback, base current of the power 
transistors is substantially proportional to the output 
load demand, and power dissipation is thus nearly pro- 
portional to the load to maintain efficiency reasonably 
high and constant despite load variation. 
The first type of circuit has another disadvantage on 
comparison to that of the second type under some over- 
load conditions, such as when any one of the paralleled 
outputs of the entire inverter system short circuits. In 
that event, the affected inverter module must be able to 
sustain the temporary overload until a protective fuse in 
series with the load opens, but since there is no feedback 
arrangement to control the base drive, the power tran- 
sistor may not saturate and this can result in transistor 
failure because of excessive power dissipation in the 
collector-emitter regions. The circuit could be designed 
to provide sufficient base current capacity for driving 
the overload, but if that is done, total system efficiency 
is decreased. 
If, on the other hand, a feedback arrangement is pro- 
vided to control the base drive with individual output 
current feedback, as shown in FIG. 1 the result is un- 
equal current sharing among power transistors, particu- 
larly during the power transistor turn-on period since 
each then has its own feedback control. Assuming an 
arrangement in which N modules are used, each with a 
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4,222,098 
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and the present invention, which is the arrangement for tors of the other modules, the failed module would 
providing composite feedback for all modules, as shown become an almost short-circuited load for the entire 
in FIG. 2, as opposed to individual feedback for each inverter s , and this could produce total system 
module as shown in the prior-art arrangement of FIG. failure. 
1. By the improvement of FIG. 2, wherein the primary 
Referring now to FIG. 1, a plurality of inverter mod- winding 12 of the current pulse transformer Ti in the 
ules 1. . , N are shown for inverting power from a direct base drive circuit of each of the modules is used for a 
current source, VDC, into a common load 10 at a fre- composite positive feedback from all modules, it is 
quency controlled by clock input signal. Each module is made certain that each power transistor will be driven 
comprised of a pair of power transistors QA and QB 10 into saturation on any overload condition which affects 
which are alternately turned on by base drive circuits any of the modules, making it possible for any affected 
comprised of switching transistors Qi and Q2. The ar- transistor to withstand overload stress until a protective 
rangement is such that the power transistor QA of all of fuse iti series with the load opens. While this does not 
the modules are on during the same time while the improve basic load sharing among the modules, it does 
switching transistors Qi of the modules are on, and all of 15 prevent high spike generation during turn-on of the 
the power transistors QB are on while the switching faster switching transistor and prevent undesirable sys- 
transistors 4 2  are on. In that manner, all of the modules tem oscillation. Moreover, any means provided for 
are controlled in parallel by a common clock input automatically equalizing load sharing and current bal- 
signal. However, since it is not feasible to match all ancing overthe main portion of each current delivering 
switching transistors it is possible for one of the power 20 half cycle of the clock input signal is not degraded with 
transistors, such as the transistors QB of module 1, to this new arrangement. On the contrary, this new ar- 
turn on faster than the power transistor QB of another rangement exerts a beneficial effect on load sharing 
module so that one module will tend to provide more during the short period following turn-on to minimize 
current to the load than other modules. unequal turn-on characteristics of the power transistors. 
The arrangement of FIG. 1 which utilizes individual 25 This may be appreciated from the following descrip- 
current feedback from the output circuit of each mod- tion. 
ule to its own power transistor base circuits via a pri- Assuming that transistor QA of module 1 is turned on 
mary winding 12 of a current pulse transformer TI, base faster than transistor QA of module N, current 11 in 
current is substantially proportional to the output load module 1 will be larger initially than current INin mod- 
demand, and power dissipation is thus nearly propor- 30 ule N. However, currents will equalize very quickly 
tional to loading. Efficiency is therefore reasonably due to the fact that both modules develop the same 
high and constant despite load variations. In a circuit feedback current from the same load current 1~ equal to 
having no feedback, the base current of power transis- the sum of all of the module currents 11. . . IN. In that 
tors is held constant regardless of the output load. manner, all of the power transistors are driven by the 
Therefore power dissipation in the base circuit is the 35 same amount of base current regardless of initial switch- 
same regardless of the load value, and thus efficiency ing response differences. Furthermore, total system 
degrades on lighter loads. The individual feedback ar- oscillation due to a primary winding open circuit in one 
rangement is thus superior to no feedback, but it has the of the current pulse transformers cannot occur as in the 
disadvantage that it tends to emphasize unequal current prior art having individual output current feedback to 
sharing among power transistors, particularly during 40 the base drive circuit of each module. This is apparent 
the power transistor turn-on period. Note that in this from the following description. 
arrangement power transistors QB are on in each mod- The total base drive current for the power transistors 
ule during the same period. However, if a transistor QB is made up of two components: the triggering base cur- 
starts to turn-on faster than another corresponding tran- rent IT, which may be expressed as IT=Nl(VC--- 
sistor, the feedback current of the power transistor 45 VBE-VD)/RC; and the feedback current IFwhich may 
turned on faster is larger than that of the other module be expressed as I,v=N~I~,, in which N1 designates the 
because of transistor response time differences. There- current transformer turn ratio for the clock input pulse, 
fore, the transistor turned on first is accelerated to turn- N2 designates the turn ratio for the third (feedback) 
on further during the slower turn-on of the transistor of winding 12, Ir, is the load current, and Vc, V ~ ~ a n d  VD 
the other module. This results in high spike generation 50 are respectively the collector voltage drop and base- 
during turn-on of transistor which turns on first. Such emitter voltage drop of the power transistor, and the 
an effect might stress the fast switching transistor suffi- voltage drop across the forward biased diode D1. Note 
ciently to produce failure due to the second breakdown that the secondary winding of each output transformer 
effect. T2 is connected in parallel with the secondary winding 
Moreover, the arrangement of FIG. 1 can cause un- 55 of the output transformer of every other module con- 
desirable system oscillation in the event of open-circuit- nected in parallel with the load. If by design the trigger- 
ing of the primary winding of one of the switching ing base current I ~ i s  set slightly higher than the feed- 
transformers TI. In normal operation, the “on” and back current IF under normal load conditions, and the 
“off” periods of the power transistors are controlled by primary winding of transformer Ti happens to open, the 
the input clock frequency. If, for example, one winding 60 failed module would attempt to go into self-oscillation 
of transformer T1 opens, the periods are no longer con- at a frequency controlled by the core saturation time 
trolled by the clock frequency but instead depend upon constant of the current pulse transformer Ti. However, 
the saturation time constant of transformer Ti. The the other modules in the inverter system would not be 
module housing that failure would then go into self- effected by the attempted self-oscillation because the 
excited oscillation at a frequency which has no relation- 65 triggering current IT which is controlled by the clock 
ship to the normal clock drive rate. This could be disas- frequency, is larger than the feedback current IF. The 
trous; unless the affected power transistor happens to clock frequency thus continues to control the frequency 
turn on at the same time as all the corresponding transis- of operation in each of the other uneffected modules. 
5 
4,222,098 
5 6 
These other uneffected modules will produce the com- 2. An improved base drive arrangement for power 
mon feedback signal which is then applied to all mod- transistors in paralleled inverter modules connected to a 
ules, including the failed module, and since this feed- common load comprising means for deriving substan- 
back signal includes the effect of the clock, it will force tially equal positive feedback currents for all modules 
the operating frequency of the failed module to coincide 5 from the total load current, and 
with the clock drive. Thus normal frequency operation means for combining said positive feedback currents 
of the failed module will occur even with its open-cir- with base drive currents for the power transistors 
cuited primary winding. Because the triggering circuit of each of the modules, where said base drive cur- 
may be set much lower than the constant base drive rents are derived from a common clock pulse sig- 
current of the same circuit without any feedback under 10 nal. 
normal load conditions the total system efficiency of 3. The improvement defined by claim 2 wherein said 
this new arrangement is significantly better than for base drive currents for power transistors of all modules 
paralleled modules without this new arrangement. are set substantially equal and only slightly higher than 
Although a particular embodiment has been illus- the derived feedback currents so that, under overload 
trated and described, it is recognized that modifications 15 conditions, the feedback current to a power transistor of 
and variations may readily occur to those skilled in the any one module can affect control over the base drive 
art. Consequently, it is intended that the following current of the power transistor. 
claims be interpreted to include such modifications and 4. The improvement defined by claim 3 wherein base 
variations. drive currents to power transistors of said modules are 
20 coupled to said power transistors by current pulse trans- 
formers, and wherein said combining means for each 
module is comprised of a separate winding on said cur- 
rent pulse transformer connected in series with said 
load. 
5. The improvement defined by claim 4 wherein each 
module includes two power transistors and said current 
pulse transformer includes two primary windings and 
two secondary windings for alternately driving on said 
two power transistors. 
What is claimed is: 
1. In an inverter system having a plurality of inverter 
modules connected in parallel to a load for inverting 
power from a source through power transistors under 
control of a clock input signal, the improvement com- 
prised of a positive feedback current derived from the 25 
total current to the load from all of the modules of the 
inverter system and applied to the base drive of each of 
the power transistors of all modules thereby providing 
all modules protection against open or short circuit 
faults occuring in any of the modules. * * * I *  30 
3s 
40 
45 
so 
5s 
65 


Base drive for paralleled inverter systems

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