Shift register was developed which uses only one D type flip-flop and improves packaging density by approximately 25% over the usual arrangement. Circuit is compromise between full master-slave arrangement and dynamic shift register, with limitation only of length of time that clock can be held high during new data entry

Pryor, R. L.

Smith, A. M.

English

NASA Technical Reports Server

September 1972
	
B72-10591 
NASA TECH BRIEF 
NASA Headquarters	
A 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage 
commercial application. Tech Briefs are available on a subscription basis from the National Technical Information 
Service, Springfield, Virginia 22151. Requests for individual copies or questions relating to the Tech Brief program may 
be directed to the Technology Utilization Office, NASA, Code KT, Washington, D.C. 20546. 
A Simplified, Compact Static Shift Register 
The problem: 
The large number of field-effect elements used in 
flip-flops employing the full master slave principle 
requires many components and results in a high pack-
aging density. 
The solution: 
A static shift register stage has been developed 
which uses only one D Type flip-flop rather than the 
usual flip-flop pair in a master-slave arrangement. This 
new arrangement improves , packaging density by ap-
proximately 25%. 
How it's done: 
The clock in the illustrated circuit is normally low. 
In this condition, the transmission gate (Ti and T2) is 
conductive and transmits the datum content of the 
previous stage through input D to the storage node, 
which is so labeled in the circuit diagram. With the 
clock low, the two inner series devices in the first in-
verter, T5 and T6, are nonconductive, disabling the first 
inverter which has the new data content ready on the 
two outer devices, T3 and T4. The second inverter 
(which is activated due to the inner devices, T9 and Ti 0, 
being conductive) and the third inverter are connected 
back to back to form a flip-flop which is holding the 
previously stored datum; this information may be either 
a ,I,, or a ''0" 
When the clock goes high, the transmission gate 
(Ti and T2) becomes nonconductive, preserving the 
datum at the time of clock rise at the storage node, 
which is now isolated from input D.
Simultaneously the second inverter is disconnected 
from the supply voltages by the transition to a non-
conductive state of T9 and TI 0. Its output and the out-
put of the first inverter are tied together, and the first 
inverter has now become operative through the transi-
tion to a conductive state of T5 and T6. The iatchnig 
action of the flip-flop is no longer operative under these 
conditions. The new datum at the storage node has now 
replaced the old datum at the outputs. The inverse of the 
datum entered at D (supplied by the first inverter) now 
appears at 7Q, and the direct datum (re-inverted by the 
third inverter) appears at Q. 
When the clock returns to low, the proper logic level 
for the new datum is already controlling T7 and T8 in 
the second inverter, which is becoming activated again 
through the conductance of T9 and Tb. With the latch 
reactivated, the datum which was entered when the 
clock became high is now stored. A new datum can 
once again enter the storage node which is once again 
isolated from the flip-flop. 
In effect, this circuit is a compromise between a 
full master-slave arrangement with two complete static 
flip-flops and four double transmission gates and a 
dynamic shift register which cannot provide permanent 
storage. Thus, the advantages of each conventional 
circuit are utilized without the disadvantages. The only 
time dependent limitation is in the length of time that 
the clock can be held high during the entry of new data. 
The saving in component area over a full master-slave is 
considerable since there are only 12 transistors as 
opposed to 16.
(continued overteaf) 
This document was prepared under the sponsorship of the National
	 Government assumes any liability resulting from the use of the 
Aeronautics and Space Administration. Neither the United States
	 information contained in this document, or warrants that such use 
Government nor any person acting on behalf of the United States
	 will be free from privately owned rights.
https://ntrs.nasa.gov/search.jsp?R=19720000590 2020-03-17T03:35:24+00:00Z
[I]
H Hn T4 T8
Clock
Storage
-t
O 
T11 
P
II	 Q
T12 I  
+10V 
T3	 I T7	 - 
T 1 _	 I	 T 
PruI	 I	 I 
iiTransmission	 First	 Second	 Third 
Gate	 Inverter	 Inverter	 Inverter 
Clock 
Note:	 Patent status: 
Requests for further information may be directed to:
	 NASA has decided not to apply for a patent. 
Technology Utilization Officer 
NASA Headquarters 	 Source: Richard L. Pryor and Allan M. Smith of 
Code KT
	 RCA Corp. 
Washington, D. C. 20546
	 under contract to 
Reference: B72-10591
	
	 NASA Headquarters 
(HQN-10723) 
14 V1 3 - 
Ri. 1313 
K3 
B72-10591	
.1—	 Category 02 


A simplified, compact static shift register

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