A circuit for suppressing parasitic oscillations across an inductor operating in a resonant mode is described. The circuit includes a switch means and resistive means connected serially across the inductor. A unidirectional resistive-capacitive network is also connected across the inductor and to the switch means to automatically render the switch means conducting when inductive current through the inductor ceases to flow

Fowler, J. T.

Raposa, F. L.

English

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WASHINGTON, D.C. 20546
REPLY TO
ATTN OF:
(NASa-Case-EBC-10403-1) PABASITIC
SUPPBESSING CIRCUIT Patent (NAS£) 4 p
CSCL 09C
N73-26228
Unclas
00/10 06465
TOt RSI/Scientific & Technical Information Division
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NASA Patent Case No.
; 3 . *73 7.f /
NOTE - If this patent covers an invention made by a corporate
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Copy of patent cited above
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https://ntrs.nasa.gov/search.jsp?R=19730017501 2020-03-17T08:34:13+00:00Z
United States Patent
Fowler et al.
mi 3,737,757
[45] June 5,1973
[541
1/5J
PARASITIC SUPPRESSING CIRCUIT
Inventors: John T. Fowler, Winthrop; Frank L.
3,189,796
3,560,820
3,643,129
6/1965
2/1971
2/1972
Tipton
Unnewehr
Marsh
317/DIG 6
321/45 C
317/DIG. 6
Raposa, Concord, both of Mass.
[73] Assignee: The United States of America as
represented by the Administrator of
the National Aeronautics and Space
Administration, Washington, D.C.
[22] Filed: May 15,1972
[21] Appl. No.: 253,405
[52] U.S. Cl 321/11, 317/DIG. 6, 321/45 C
[51] Int.CI... H02m 1/18
[58] Field of Search .....317/DIG. 6; 321/11,
321/12, 13.45C
[56] References Cited
UNITED STATES PATENTS
3,614,531 10/1971 Oswald 317/DIG. 6
Primary Examiner—William M. Shoop, Jr.
Attorney — N. T. Musial, J. A. Mackin and John
Manning
R.
[57] ABSTRACT
A circuit for suppressing parasitic oscillations across
an inductor operating in a resonant mode is described.
The circuit includes a switch means and resistive
means connected serially across the inductor. A
unidirectional resistive-capacitive network is also con-
nected across the inductor and to the switch means to
automatically render the switch means conducting
when inductive current through the inductor ceases to
flow.
9 Claims, 2 Drawing Figures
i
t! -
PATENTED JUN 51973 3.737,757
r~
25
FIG. I II
t, t2t3 t4
3,737,757
1 2
PARASITIC SUPPRESSING CIRCUIT when the self-induced voltage across the inductor
ORIGIN OF THE INVENTION w M P ™ * * * for a resonant in-
The invention described herein was made by employ- ductor, a parasitic oscillation suppressor circuit which
ees of the United States Government and may be man- 5 causes substantially no degradation of the inductor 2,
ufactured or used for governmental purposes by or for which requires no external control circuitry to activate
The Government of the United States of America, it and which is passive until the end of each resonant
without the payment of any royalties thereon or there- half cycle.
for
" ,0 BRIEF DESCRIPTION OF THE DRAWINGS
BACKGROUND OF THE INVENTION
 FIG. l is a schematic drawing of circuitry embodying
The invention relates to circuitry for damping para- the invention.
sitic oscillations and is directed more particularly to FIG- 2 is a graph at waveshapes which occur in a DC
circuitry for selectively damping parasitic oscillations to AC inverter of the resonant inductor type.
appearing across resonating inductors of the type used '5
 DESCRIPTION OF A PREFERRED EMBODIMENT
in high power inverters.
Some high power inverters used for converting DC Referring now to FIG. 1, there is shown a resonant
power to alternating current utilize a resonating indue- inductor type inverter 10 enclosed in dashed lines and
tor which may be magnetically coupled to a secondary a parasitic oscillation suppressor circuit 1 1 enclosed in
winding connected to a load. The resonating inductor 20 dashed lines- The mvertor 10 comprises an mductor 12
is connected serially with a capacitor, a DC source and which has its uPPer end' as viewed in the fi8ure> con-
a switch. The switch is turned on and off at a predeter- nected through a capacitor 13 to a cathode electrode
mined rate to supply current for one half cycle of oper- 14c of a silicon controlled rectifier 14 which serves as
ation to the inductor which resonates with the capac.--
 oe
 a switch means
-
 An anode
 electrode 14* of the con-
tor each time the switch opens. This provides alternat- 25 troll«d rectifier 14 1S connected to the positive side of
ing current output to the load. At the end of each reso- a DC P°wer source «• A "W*™ side of the power
nant half cycle, parasitic oscillations may occur and s°urce] 1S ls connected via lead 16 to the lower end of
may damage or destroy solid state devices such as the *f inductor \*\the lead 16 bel"8 «™un^ as at "'
switch which is usually a silicon controlled rectifier or ,0 The inductor " 1S carr"!d on a «?« W which may als°
., ...
 JU
 carry a secondary winding 19 which serves to couple
, ., ' . •»• -,, .- . , , j electrical power from the inductor 12 to a load 20.In the past, parasitic oscillations have been damped , ,K - j , j
 L i . i .
, »• • . j •. • In order to provide voltage and current through theby connecting a resistor and capacitor in series across • _ , * , . » , • j •»• » u •
* . , . . . . - . -• •„ inductor 12 at a predetermined repetitive rate there isthe inductor which is generating the parasitic oscilla- . , , ,. .. r . « / . » • • •
_ , . . . ..
 r
 i j - j provided for the inverter 10 a timing circuit comprisesions. Such a damping circuit has several duadvan-
 35 ^^ vok ,ses which tra*smitted to a
H
 ate
tages. First the damping ,s always present across he
 electrode 14b of Ac controned rectifier 14 via a fead
inductor and will seriously degrade its Q. Additionally,
 22 tQ rendef the controlled rectifier conducting. The
in order to critically damp the parasitic oscillations rel-
 timi ,ses are of short duration However, the con-
atively low values of resistance and high values of ca-
 tro,,ed rectifier „ continues to conduct after the end
pacitance must be used. This will result m unreasonably 40
 of the timi lse until its current d below its
high power consumption and low efficiency for high holding value
power inverter circuits.
 The parasitic oscillation suppressing circuit 11 com-
OBJECTS AND SUMMARY OF THE INVENTION Prises a damping resistor 23 having its lower end con-
nected to an anode electrode 24a of a controlled recti-
It is an object of the invention to provide for the in- 45
 fier 24 which serves M a switch means for circujt n
ductor of a resonant type inductor inverter, a parasitic
 A cathode electrode 24c of the controlled rectifier 24
oscillation suppressor which has substantially no effect
 is connected by means of a iead 2s to the lower end of
on the power inductor Q when current is being supplied
 the inductor !2 thereby providing a complete current
to the inductor from the DC source and which has neg-
 path The upper end of the inductor 12 is connected to
ligible effect on the inductor Q during the resonant half 50
 an anQ(Je eiectrode of a diode 26 by means of a lead 27,
cvcle.when the current through the inductor is collaps-
 the cathode of diode 26 being connected to the upper
•'&• ' end of the damping resistor 23 which serves as a volt-
It is another object of the invention to provide appa-
 age dropping means.
ratus for critically damping ringing oscillations which Control circuitry for the switch means 24 is corn-
occur after the resonant half cycle of a power inductor 55 prised of a diode 28, a capacitor 29, a resistor 30 and
of the type utilized in a resonant inductor type DC to
 a diode 31 connected serially between the leads 25 and
AC inverter. 27 as shown in FIG. 1. A point between the diode 28
Still another object of the invention is to provide a and the capacitor 29 is connected to a gate electrode
parasitic oscillation suppressor circuit which requires 24b of the controlled rectifier 24 through a lead 32 to
no external control circuit to activate it. render the controlled rectifier 24 conducting at the end
Yet another object of the invention is to provide a of each resonant half cycle of the power inverter 12 as
parasitic oscillation suppressor circuit for a resonant will be explained presently. A time constant for the dis-
inductor inverter which circuit does not draw a signifi- charge of capacitor 29 is established by a resistor 33
cant amount of power from the power inductor.
 65 connected in parallel relationship to the serially con-
An additional object of the invention is to provide a nected diode 28 and capacitor 29.
parasitic oscillation suppressor circuit which is passive To eliminate false triggering of the controlled recti-
until the end of each resonant inductor cycle, that is, fier 24, a resistor 34 is connected between the gate
3
3,737,757
electrode 24b and the lead 25. The parasitic oscillation
suppressing circuit 11 is completed by a capacitor 35
connected between the anode electrode 24a and the
cathode electrode 24c of the controlled rectifier 24.
The capacitor 35 suppresses voltage spikes which could 5
possibly damage or destroy the controlled rectifier 24.
Operation of the foregoing circuitry will not be de-
scribed. Referring to FIG. 2A, there is depicted a trig-
ger pulse 36 which is supplied at time t, to the gate
electrode 14i> by the timing circuit 21 of FIG. 1. The 10
pulse 36 renders the controlled rectifier 14 conducting
causing a voltage pulse as illustrated at 37 in FIG. 2B
to appear at the upper end of the inductor 12 with re-
spect to ground 17. When the capacitor 13 becomes
fully charged, the voltage across the inductor 12 re- 15
verses producing a voltage pulse as shown at 38 in FIG.
2B. At the end of the inductive half cycle which pro-
duced voltage pulse 38, spurious oscillations as shown
at 39 will be produced because of the rapid turn off of
inductor 12. These oscillations, as indicated previously, 20
can destroy solid state components such as the silicon
controlled rectifier 14. The current through the induc-
tor during the existence of pulses 37 and 38 is shown
at 40 in FIG. 2C. Current oscillations 41 correspond to
the parasitic voltage oscillations 39 of FIG. 2B. 25
The desired voltage waveshape for inductor 12 is
shown in FIG. 2D and comprises the voltage pulse 37
produced by current supplied to the inductor while the
'controlled rectifier 14 is conducting during r, to tz and
the voltage pulse 39 which occurs during the inductive 30
half cycle /2 to t3. As shown at 42, the voltage across the
inductor 12 is permitted to become only slightly posi-
tive at the end of the voltage pulse 39 and does not
again become negative during the cycle of operation
which ends at t4. 35
During the inductive cycle, the lower end of the in-
ductor 12 is positive with respect to its upper end as
shown by the voltage pulse 39 of FIG. 2. Consequently,
current flows from the lower end of the inductor 12
through the diode 28 to the lower side of capacitor 29. 40
Current flows from the upper side of capacitor 29
through the resistor 30, the diode 31 and the lead 27
to the upper negative end of inductor 12.
At *3, the end of the inductive cycle, the voltage
across the inductor 12 decreases very rapidly towards
0 as indicated at 43 in FIG. 2D. Capacitor 29 immedi-
ately discharges into the gate electrode 24B of the con-
trolled rectifier 24 rendering the latter conducting. At
this time the upper end of the inductor 12 is beginning
to become positive but, because of the conduction of
controlled rectifier 24 which effectively connects the
damping resistor 23 across inductor 12, only a small
positive voltage appears across the inductor as indi-
cated at 42 in FIG. 2D. Thus, the parasitic oscillation
which would normally appear across the inductor 12 at
the end of the inductive half cycle are critically damped
when the damping resistor 23 is connected across the
inductor 12 by the conduction of the controlled recti-
fier 24.
From the foregoing it will be seen that, during the
conduction of the. controlled rectifier 14, in accor-
dance with the invention, a parasitic oscillation sup-
pression circuit 11 draws no power from the inductor
12 other than a slight current due to the presence of a
protective capacitor 35. After the controlled rectifier
14 turns off to begin the inductive half cycle, the only
power drawn from the inductor 12 is that resulting by
55
60
the current required to charge the capacitor 29 of the
parasitic oscillation suppression circuit 11. Advanta-
geously, the damping resistor 23 absorbs power from
the inductor 12 only when it is desired that parasitic os-
cillation be critically damped and its insertion in the
circuit is accomplished automatically without any exr
ternal timing circuits.
It will be understood that changes and modifications
may be made to the above described circuitry by those
skilled in the art without departing from the spirit and
scope of the invention as set forth in the claims ap-
pended hereto.
What is claimed is:
1. A parasitic oscillation suppressor for use with a
power inductor of a resonant type inverter, said sup-
pressor comprising:
switch means having power electrodes and a control
electrode; first voltage dropping means connected
serially with said power electrodes of said switch
across said power inductor;
second and third voltage dropping means connected
serially between one end of said power inductor
and the other end of same;
first unidirectional conducting means and first energy
storage means connected serially in the order men-
tioned between said one end of said power inductor
and a point intermediate said second and third volt-
age dropping means; and
means connecting a point intermediate said first uni-
directional conducting means and said first energy
storage means to said control electrode of said
switch means.
2. The circuit of claim 1 wherein said first, second
and third voltage dropping means are resistors.
3. The circuit of claim 1 and including a second uni-
directional conducting means connected between said
third voltage dropping means and said other end of said
power inductor and poled to pass current in the same
direction as said first unidirectional conducting means.
4. The circuit of claim 3 wherein said switch means
is a solid-state controlled rectifier having anode, cath-
ode and gate electrodes.
5. The circuit of claim 4 and including second energy
storage means connected between said anode and said
cathode of said controlled rectifier, and third unidirec-
tional conducting means connected in series with said
first voltage dropping means between said second en-
ergy storage means and said other end of said inductor,
said third unidirectional conducting means being poled
to pass current in the same direction as said SCR.
6. The circuit of claim 5 and including fourth voltage
dropping means connected between said gate electrode
and said one end of said power inductor. <
'7. The circuit of claim 5 wherein said first and second
energy storage means are capacitors. .
8. The circuit of claim 5 wherein said first and secoi^
unidirectional conducting means are solid-state diodes.
9. A parasitic oscillation suppressor for use with a
power inductor of a resonant type inverter, said sup-
pressor comprising
switch means having power electrodes and a control
electrode; first voltage dropping means connected
serially with said power electrodes of said switch
across said power inductor;
a first capacitor connected to said control electrode
of said switch means;
means for charging said capacitor during the induc-
tive half cycle of the power inductor; and
means for limiting the discharge rate of said capaci-
tor whereby the discharge time of said capacitor is
of adequate duration to render said switch means
conducting.


Parasitic suppressing circuit

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