Published document discusses method for correcting errors. According to this method, computer operation becomes fault-tolerant, i.e., its operation is error-free in spite of single hardware element malfunction. Also, method provides for detection and correction of repetitive and spurious processing and transmission errors

Campbell, R. D.

English

NASA Technical Reports Server

V	 September 1974	 B74-10147 
NASA TECH BRIEF 
.. Marshall Space Flight Center 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage 
commercial application. Tech Briefs are available on a subscription basis from the National Technical Information 
Service. Springfield, Virginia 22151. Requests for individual copies or questions relating to the Tech Brief program may 
be directed to the Technology Utilization Office, NASA, Code KT, Washington, D.C. 20546. 
Error-Correcting Codes for High-Speed Digital Computers 
.
A document has been published which discusses a 
method for the correction of errors in high-speed 
digital computers. These errors result from the occasional 
failures within the computer hardware. According to 
this method, the computer operation becomes fault-
tolerant, i.e., its operation is error-free in spite of a 
single hardware element malfunction. 
A logic circuit operates according to a prescribed 
matrix to generate a code vector derived from parity 
bits according to the information bits processed. Each 
row of the matrix corresponds to one partition of the 
code vector which, in turn, corresponds to one segment 
of the hardware. The parity bits are set when the vector 
is created, to establish even parity for each matrix 
column. Bit inversions which occur, due to hardware 
failures, will cause a unique pattern when parity checks 
are reconstructed, permitting the logic circuit to restore 
the original vector. 
The error corrector circuit may be contained on a 
single integrated circuit chip. The chip will reconstruct 
parity, analyze the pattern formed, and correct any 
erroneous information bits.
Notes: 
1. The method provides for the detection and correction 
of repetitive and spurious processing and transmission 
errors. 
2. Requests for further information may be directed to: 
Technology Utilization Officer 
Marshall Space Flight Center 
Code ATO1 
Marshall Space Flight Center, Alabama 35812 
Reference: B74-10147 
Patent status: 
NASA has decided not to apply for a patent. 
Source: R. D. Campbell of 
Sperry Rand Corp.
under contract to

Marshall Space Flight Center
(MFS-22887) 
Category 02 
.
This document was prepared under the sponsorship of the National 
Aeronautics and Space Administration. Neither the United States 
Government nor any person acting on behalf of the United States
Government assumes any liability resulting from the use of the 
information contained in this document, or warrants that such use 
will be free from privately owned rights.
https://ntrs.nasa.gov/search.jsp?R=19740000147 2020-03-17T14:06:14+00:00Z


Error-correcting codes for high-speed digital computers

Abstract

Similar works

Full text

Available Versions

NASA Technical Reports Server