Module contains mask register, line register, primary sync register, secondary sync register, push-pop stacking register, control section, and interrupt address generator. APIM operates in conjunction with logic found in majority of minicomputers to provide fully-vectored interrupt capabilities

Jeane, H. L.

English

NASA Technical Reports Server

NASA TECH BRIEF 
NASA Pasadena Office N' . , JA is
September 1974	 B74-10165 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage 
commercial application. Tech Briefs are available on a subscription basis from the National Technical Information 
Service, Springfield, Virginia 22151. Requests for individual copies or questions relating to the Tech Brief program may 
be directed to the Technology Utilization Office, NASA, Code KT, Washinglon, D.C. 20546. 
Advanced-Priority Interrupt Module 
.
• The advanced-priority interrupt module (APIM) fabri-
cated on a single wire-wrap circuit board provides 
minicomputers with an interrupt structure comparable 
to that found on larger and traditionally more sophisti-
cated computers. The module contains a mask register, 
a line register, a primary sync register, a secondary sync 
register, a push-pop stacking register, a control section, 
and an interrupt address generator. Tle APIM operates 
in conjunction with the logic found in the majority of 
minicomputers to provide fully-vectored interrupt capa-
bilities. 
The APIM contains an array of approximately 
140 IC's, the majority of which are registers which 
receive, synchronize r
 and process the interrupt signals 
from external sources. The APIM scans the interrupt 
lines at approximately 900-ns intervals. If signals occur 
on more than one interrupt line during any 900-ns 
scan period, the highest priority signal is acknowledged. 
The remaining interrupt requests are stored in the line 
register until each has been acknowledged. At the end of 
each 900-ns period, a request is sent to the control logic 
which in turn generates a request for an interrupt from 
the computer. The priority level of a device connected 
to the interrupt module is determined by channel 
selection at the time of installation. 
The push-pop stacking register of the APIM dy-
namically stores information that allows the scheduling 
of interrupts without extensive software overhead. 
Minimal masking and no enabling or disabling of 
interrupts are required by the stored software program. 
An arriving interrupt of high priority causes a lower
priority subroutine to cease operations. After the higher 
level routine is processed, information stored within the 
stacking logic permits a return to the lower priority 
subroutine. A lower level interrupt is precluded from 
interrupting higher priority processing. 
The circuit board also includes control logic circuits 
which vary slightly in format with the make and model 
of minicomputer. The modification of these circuits will 
adapt the module to specific minicomputers. Although 
the module provides 16 levels of priority, the design 
permits expansion to 128 channels. 
Note: 
Requests for further information may be directed to: 
Technology Utilization Officer 
NASA Pasadena Office 
4800 Oak Grove Drive 
Pasadena, California 91103 
Reference: TSP74-1 0165 
Patent status: 
Title to this invention has been waived under the 
provisions of the National Aeronautics and Space Act 
[42 U.S.C. 2457 (f)], to the California Institute of 
Technology, Pasadena, California 91109. 
Source: Harvey L. Jeane of

Caltech/JPL
under contract to

NASA Pasadena Office

(NPO-1 3067) 
Category 02 
This document was prepared under the sponsorship of the National 	 Government assumes any liability resulting from the use of the 
Aeronautics and Space Administration. Neither the United States 	 information contained in this document, or warrants that such use 
Government nor any person acting on behalf of the United States
	
will be free from privately owned rights.
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Advanced-priority interrupt module

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