Synchronous phase-lock-loop detector accepts distorted input and generates jitter-free clock. Data-detection circuitry takes advantage of this clock and employs integrate-and-dump decision circuit to provide near-theoretically ideal data decoding

Balliet, L.

English

NASA Technical Reports Server

October 1973	 B73-10323 
•	 NASA TECH BRIEF 
Marshall Space Flight Center 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage 
commercial application. Tech Briefs are available on a subscription basis from the National Technical Information 
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be directed to the Technology Utilization Office, NASA, Code KT, Washington, D.C. 20546. 
Synchronous Ten-Megabit Biphase Detector 
Distorted 
	
Biphase 
	 I
Precondition 	 Phase Lock 
	
Input from	 Logic 
	 I	
Loop 
MODEM
Clock	 '1
To 
Terminal 
Integrate-	 Logic 
and-Dump	 NRZ Data 
Detector 
Signal Conditioning Data Flow 
The problem: 
In the Space Station data-management system, ten 
megabit biphase data is frequency-division multiplexed 
(FDM) over a coaxial cable data bus. A model of the 
system is now under concept verification testing. The 
FDM process requires MODEMS (modulator/demodula-
tors) that employ filters for channel selection. Distortion 
is caused by these filters as well as by couplers and im-
perfect cable and circuitry. The distorted data makes it 
impossible to generate a jitter-free clock directly from 
the data and correctly decode the biphase signal. 
The solution.: 
A synchronous phase-lock-loop detector was designed 
to accept the distorted input and to generate a jitter-free 
clock. The data-detection circuitry takes advantage of 
this clock and employs an integrate-and-dump decision 
circuit to provide near-theoretically ideal data decoding. 
How it's done: 
The 10-MHz biphase data is accepted by the synchro-
nous detector and is preconditioned by differentiation 
and rectification logic (see figure). 
This logic generates a short pulse for each data tran-

sition and consequently produces a frequency spectrum
to the phase-lock-loop that contains continuous-fre-

quency components. The phase-lock-loop synchronizes 
. 
to the 20-MHz component and accordingly locks to the
phase of the incoming data. The phase-lock-loop pro-
vides filtering and does not follow the instantaneous 
transition variations of the distorted data. The 20-MHz 
output is "divided by two" to produce the required 
10-MHz jitter-free clock output. Advantage is taken of 
the nearly ideal phase-lock-loop clock to implement an 
integrate-and-dump data detector. 
Notes: 
Requests for further information may be directed to: 
Technology Utilization Officer 
Marshall Space Flight Center 
Code A&PS-TU 
Marshall Space Flight Center, Alabama 35812 
Reference: B73-10323 
Patent status: 
Inquiries concerning rights for the commercial use of 
this invention should be addressed to: 
Patent Counsel 
Marshall Space Flight Center 
Code A&PS-PAT 
Marshall Space Flight Center, Alabama 35812
Source: L. Balliet of

IBM Corp.
under contract to
Marshall Space Flight Center

(MFS-22546) 
is
Category 02 
This document was prepared under the sponsorship of the National
	 Government assumes any liability resulting from the use of the 
Aeronautics and Space Administration. Neither the United States
	 information contained in this document, or warrants that such use 
Government nor any person acting on behalf of the United States
	 will be free from privately owned rights.
https://ntrs.nasa.gov/search.jsp?R=19730000323 2020-03-17T06:57:51+00:00Z


Synchronous ten-megabit biphase detector

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