Modified fabrication technique for P-channel MOSFET devices eliminates problems involving gate placement and gate overlap. Technique provides self-aligned gate, eliminating complexity of mask aligning. Devices produced by this process are considerably faster than conventional MOSFET's and process increases yield

Ostis, S.

Woo, D. S.

English

NASA Technical Reports Server

(c)
Formation Of Gate 
June 1973
	 B73-10197 
NASA TECH BRIEF 
Marshall Space Flight Center 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage 
commercial application. Tech Briefs are available on a subscription basis from the National Technical Information 
Service, Springfield, Virginia 22151. Requests for individual copies or questions relating to the Tech Brief program may 
be directed to the Technology Utilization Office, NASA, Code KT, Washington, D.C. 20546. 
P-Channel Silicon Gate FET 
.
The problem: 
The conventional fabrication of P-channel Metal-
Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) 
devices involves a critical step in the alignment of the 
gate metalization mask. Because of this, fabrication of 
large arrays of nonredundant devices on single wafers 
has proven difficult. The problem is that a design 
tolerance must be built into the system to allow for a 
slight misalignment. This usually leads to an 8- to 10-pm 
gate overlap above the source and drain regions, increas-
ing the gate capacitance which limits the speed of the 
MOSFET. 
The solution: 
A modified fabrication technique for the P-channel 
MOSFET devices eliminates the problems involving gate 
placement and gate overlap.
Si Poly (0.5 /An)
How it's done: 
The entire process, as shown in the figure, involves 
six steps. First, the device area is isolated on the silicon 
N-type substrate (step a). Immediately after the clean 
gate oxide is grown, the layer is covered and protected 
by a polycrystalline silicon layer (step b). Next, the gate 
is formed (step c). The gate electrode and source and 
drain regions are then simultaneously diffused, and thus 
are geometrically well defined (step d). Further lateral 
diffusion of the P+ doped regions is kept at a minimum 
by limiting the temperature in the remaining processing 
steps. The final steps (e) and (f) are deposition of the 
oxide passivation layer and formation of metalization 
contacts, respectively. 
This technique provides a self-aligned gate, eliminating 
the complexity of mask aligning. The source and drain 
electrodes are formed exactly as required with a lateral 
diffusion equal to the depth of diffusion, 0.5 pm. 
(a)
Isolation Of Device Area 
P + Diffusion
Gate Oxide (0.1 pm) 
'1,zJj 
Si IN Type) 
(b)
Growth Of Gate Structure 
Oxide Passivation Layer
Si 02 (1 prii) 
Device Area 
Si (N Type)	 I 
. 
• 
(d)
P + Diffusion
(e)	 (f) 
Passivatjon	 Metalization Contact 
(continued overleaf) 
This document was prepared under the sponsorship of the National
	 Government assumes any liability resulting from the use of the 
Aeronautics and Space Administration. Neither the United States
	 information contained in this document, or warrants that such use Government nor any person acting on behalf of the United States
	 will be free from privately owned rights.
https://ntrs.nasa.gov/search.jsp?R=19730000197 2020-03-17T07:13:59+00:00Z
Devices produced by this process are considerably 
faster than conventional MOSFET's because the parasitic 
capacitance has been reduced by at least a factor of 10. 
Since the work function of polycrystalline silicon is 
much closer to that of the single silicon substrate than 
any metalization, device threshold voltages are reduced 
by a minimum of 0.5 V, which makes it possible to use 
lower-voltage power supplies. Finally, the process in-
creases the yield because the gate oxide photoresist 
step is not as critical as in the conventional process. 
Note: 
Requests for further information may be directed to: 
Technology Utilization Officer 
Marshall Space Flight Center 
Code A&PS-TU 
Marshall Space Flight Center, Alabama 35812 
Reference: B73-10197
Patent status: 
Inquiries concerning rights for the commercial use 
of this invention should be addressed to: 
Patent Counsel 
Marshall Space Flight Center 
Code A&PS-PAT 
Marshall Space Flight Center, Alabama 35812 
Source: S. Ostis and D. S. Woo of 
Sperry Rand Corp.
under contract to
Marshall Space Flight Center
(MFS-22505)
. 
. 
B7310197	 Category 01


P-channel silicone gate FET

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