Bistable multivibrator circuits operating at high speed and low power dissipatio

Winkler, T.

English

NASA Technical Reports Server

https://ntrs.nasa.gov/search.jsp?R=19710006435 2020-03-17T02:41:17+00:00Z
Nov. 1, 1966 JAMES E. WEBB 3,283,175 
ADMINISTRATOR O F  T H E  NATIONAL AERONAUTICS 
A N D  SPACE ADMINISTRATION 
A.C. LOGIC FLIP-FLOP CIRCUITS 
Fi led  Jan. 8, 1964 2 Sheets-Sheet I 
Nov. 1, 1966 JAMES E. WEBB 3,283,175 
ADMINISTRATOR OF T H E  NATIONAL AERONAUTICS 
A N D  SPACE ADMINISTRATION 
A.C. LOGIC FLIP-FLOP CIRCUITS 
Fi led  Jan. 8, 1964 2 Sheets-Shset 2 
CLOCK P U L S E S  
POSITIVE BIAS - CONDUCTING 
I 
CONDUCTING 3 
CONDOCTINC 7 
- - -- . - -- -- - - 
Q.2 Co~Lecrop 
UIGU POSITIVE BIAS 
L O W  POSITIVE S I P S  UNABLE TO CONDUCT 
READY TO CONDUCT 
Qs BASE 
LOW POSITIVE BlPS 
R k A D Y  TO CONDUCT ! \  6 
Q4 BASE t 2 TIM= 
t 1 __C TED X I N ~ L L E ~  
INVEhlTOR. 
3,283,175 United States Patent Ofice ,a,,, , 
1 2 
3,283,175 FIG. 1 is a schematic diagram of the invention as ern- 
A.C. LOGIC FLIP-FLOP G I R C m S  ployed in a computer logic circuit. 
James E. Webb, Administrator of the National Aeronau- FIG. 2 is a schematic diagram of a fiipfiop cin:uit 
tics and Space Administration, with respect to an inven- according to the invention. 
tion of Ted Winkler 5 FIG. 3 is a waveform timing chaH of assistance in 
Filed Jan. 8, 1964, Ser. No. 336,607 the exposition of the invention. 
4 Claims. (CI. 307-88.5) Referring to FIG. 1 there is shown a poxZion of a corn- 
?his invention relates to bistable multivibrator or uffip- puter logic circuit 2 t o  illustrate uuse: of the "ap-flisip"" 
flop" circuits and has particular reference to such a cir- circuits- 
cuit which is characterized by and low power 10 Elements numbered 4, 6 and 8 represent individual 
dissipation. identical flip-flop circuits of this invention. The Bipllop 
is  we^ known to those versed in the art, a flip-flap circuits are connected to a gate 10 comprising " A N W  
con~prises a bistable multivibrator consisting normally l2, 149 "OR" l6 and resistor :rh2 
of two acbive devices, such as transistors, interconnected "AND" diodes are connected to output terminals 2@ af 
by electric networks. The portion of the output voltage l5 elements and and the ' ' O r  diode to hput 
of each is applied to the input of the other and is of such 22 of element 8. Other gates would in tuna be connec.ted 
fixed magnitude and polarity as to maintain the devices to Output terminals 24 and input terminds 26 respec~~~ely ,  
alternately conducting over controllable periods of time. A clock pulse (CP) is applied to gate 10. Clock pulse 
ne voltage waveform from the output of each of the current will be directed 2hrOugh the "OPC"' diode 1161 to 
devices is essentially rectangular in form. Either of the 20 input terminal 22 only if d l  "AND" diodes Xi? and 14 
two devices may remain conducting with the other non- are connected to flipflop OdpUtS 20 that are in the ""htre'" 
conducting, until the application of an external triggering o r  off condition. The clock pulse current will m'?l ih 
pulse. Flip-flops play an important role in the arithme- directed to  the "OR" diode and terminal 22 if -r"ither or 
tic operatioxls of digital computers, in modern frequency both of  the flip-flop circuits of the "AND" diQdes lie, 14 
and time measuring equipment, and in various circuit 25 are in a "false" o r  on condition. 
combinations in many data handling systems. Looking now at FIG. 2, there is shown a typical em- 
There are many a~plications for a flip-flop capable of bodiment of the present invention which may employ a 
high-speed transition between stable states. Generally pair of silicon transistors Q1 and 42 as the active swirch- 
the rapidity of the transition from one stable state to  ing elements and a pair of grmanium transistors Q3 and 
another is detr;imentally affected by the circuit from 30 Q I  as emitter- follower^. While the preferred ernbMi- 
which the triggering input pulse is derived and, in fact, ment employs both sitlicon and germaniunr transistors, if 
that circuit may be such as to render the triggering un- should be understood that the circuit may be modified 
reliable in the event that the triggering pulse is of very to incorporate all silicon transistors, as will become ap- 
short duration. Also, since very large numbers of ap-flop parent hereinafter. The flipilop circuit includes transis- 
circuits are employed in many digital computer systems 35 tors Q1 and 42, both of which are npn typs ,  baliini: 
it is desirable to minimize the power consumption of the their emitters connected to a c o r n o n  diode 15. Diode 
individual circuits. In accordance with the present in- 15 provides a slighst voltage drop to p v i d e  a ~ositive 
vention, these objectives are accomplished by providing potential a t  its anode which may, for  example, be 0016 the 
a flip-flop incorporating a cascaded emitter-follower and 40 order of +0.6 volt. This source of ptenl ial  appears at 
which has exceptional high-speed and low power dissi- terminal 28. Criss cross connections 30 and 32 con~nect 
pation. the collectors of  transistors 42 and Q% through resist- 
It  is therefore, the principal object of the invention to ances 34 and 36 lto the bases of transistors Q3 and Q4, 
provide a novel and improved flip-flop oircuit and method respectively. The collectors of pnp transistors 43 and 
of operation whereby the operating time of the circuit 45 Q4 are grounded. The bases of transislors Q1 and Q2 
and the power dissipation thereof are significantly re- are referenced to ground 38 through resistanm 40 and 
duced. 42, respectively. Load resistors 44 and 46 are connel:ted 
Another object of the invention is to provide a novel to positive supply terminal 48, which may have a wtem- 
and improved flip-flop circuit employing cascaded emitter- tial of the order of f 6 vol'ts amlied thereto. As can 
followers. be seen, in this embodiment no negative power sup1)lies 
Still another object of the invention is to provide a are necessary. Load resistors 44 and 46 are mnnei-led 
novel and improved flip-flap circuit which employs A.C. to the bases of transistors Q1 and Q2 t h m g h  diode:; 50 
logic and which is capable of extremely rapid transition. and 52, respectively. Diodes 50 and 5% are preferably 
Another object of the invention is to provide a novel of the silicon type. The input terminals 20 the resjlwc- 
and improved flip-flop circuit employing solid state active 55 tive bases of transistors Ql and 4 2  are idicated at 22 
devices. and 26, and in accordance with the invention there are 
It is yet another object of she invention to provide a interposed between these terminals and the bases of the 
novel and improved flip-flop circuit which does not re- respective transistors Q1 and 42 diodes 54 and 56 which 
quire both positive and negative power supplies. may be of the silicon type. The emiMer of transistor 43 
Still another object of the invention is the improvement is connected to terminal 20 and the emitter of transistor 
of flip-flop circuits generally. 44 is connected to  terminal 24, through which the re- 
A general object of the invention is to provide a novel spective outputs of these transistors may be cpbtaiaed. 
and improved flip-flop circuit which overcomes disadvan- The function of capacitors 58 and 60 which are connected 
tages of previous means and methods heretofore intended between ground 38 and the bases of transistors Q3 and 
to accomplish generally similar purposes. 05 44, respectively, wil.1 be described hereinafter. 
Other advantages, features, and additional objects of Essentially the circuit comprises switching transistors 
the present invention will become manifest to  those versed Q1 and Q2 and transistor amplifiers 43 and 44. The 
in the art upon making reference to the detailed descrip- bases of amplifiers 43 and Q1 are biased by thlc: switc9s- 
tion and the accompanying drawings in which a preferred ing transistors Q1 and 42. 
embodiment, incorporating the principles of the present The ,impedance network comprising resismrs 40, 4, & 
invention is shown by way of illustrative example. In and 46, and diodes 50 and 52 is such that with no cur- 
the figures: Tent Slowing to the collector of one switching transistm 
3,283,176 
3 4 
( e  g. 621, the volt,rge at the base oE the se~oxrd (e.g. Q1) Iliodea 50 (5%) aiid 54 (56 )  prevent waste of riock 
ir slightly negative t+ith respect to the emitter. This is p u l s  power. Diode 50 152) blocks the positlive olock 
~liustrated at the Leginning of the waveforms identified pulse arrrent hy providi~lg a ,high irnsdar~m path to p e -  
as Qlb, Qab in FIG, 2 which indicate the change in base vent part of the cutrenl from dissipating tluo~rgh resistor 
voltage oE transistors Q1, Q2 with respect to time, using 6 44 (&), whiIe diode 54 (56) provides a vely low im- 
the emitter voltage as a reference. The current in the pedance, path. This arrangement permits a decrease in the 
collector circuit of the second transistor (Q1) causes a clock pulse current necessary to fire transistors QB (42) 
voltage drop across the collector load resistor 46, which and results in a considerable saving in power. 
in turn lowers the voltage at the base of tfhe first transis- As can be seen, amplifiers 4 3  and 4 4  remain off and 
tor (Q2) to a sufficiently negative value to continue to 10 do not use power until two events take place: (1) the 
wevent collector current flow (see the waveform indi- proper transistor Q1 ( 4 2 )  in bhe switohing circuit is 
ca%d at Q2, and Q1, in FIG. 2 which indicate the change conducting so that the correct bias is applied to the base 
*a collector voltage of these transistors with respect to of the amplifying transistor 4 3  (Q4), and (2) a clock 
time, using the emitter voltage as a reference). This pulse is applied to the emitter of the amplifying transis- 
condition of one transistor off ( 4 2 )  and the second (Q1) 15 tor. Therefore, little Power is used. 
on  will be maintained as long as the circuit remains un- The various wavefo~*ms in FIG. 3 show the tifunction 
disturbed. of the four transistors during tihe above described sequence. 
The circuit is designed to respond to A.C. logic sig- As can be seen from the foregoing description, the 
nals. In a typical application, the input to  the circuit is invention provides a flip-flop circuit which aperates at 
provided through a pair of gating structures comprising 20 a speed rn~ch higher than that heretofore realized with 
"AND" and "OR" gates which accept recurring clock flip-flop C ~ E U ~ ~ S  of similar types. Also the circuit of 
pulses from any suitable clock. In a $typical construe- the invention draws little ,power during the !interval be- 
tion, the pulses may have a positive-going polarity. tween transistions fronl State to  state. Since certain 
The gating structure is pulsed oontinuously from the clock changes may be made in the above descri,bed embodiment 
and the clock time is small cornpared to the period cuf 25 of the invention without departing 'from the scope of the 
operation of the flipaop circuit as can seen in the invention heherein involved, it is intended that all matter 
first waveform of FIG. 3. Therefore, the duty cycle of contained in the above description or  shown in the ac- 
the circuit will be smal.1 and standby ipower dissipation companying drawings shall be interpreted as illustrative 
will be kept to a minimum. and not in a limiting sense. For  example, it will be 
Refersings to FIGS. 1 and 2, the fiiMap circuit op- 30 apparent to bhose versed in the art that silicon transistors 
erates in the following manner: assume that transistors may be substituted f ~ l ~ r m a n i * ~ m  transistors 4 3  and Q4 
Q1 and Q3 are connected to the logic circuit shown in by the application of negative or  zero bias voltages to  
solid lines, transistors QZ and 44 are connected to a sec- the bases 4 3  and Q4 ad by the interposition of a 
logic cimit shown), and transistor 4 3  is con- suitable RC network into the circuit between diode S(V 
ductive. 35 (52) and load resistance 44 (46) respectively. 
The clock pulse voltage is applied across resistor 18  It  being understood that various omissions, substitu- 
and produces a clock current. ms current will flow tions and changes in the form and details of the device 
$hrough the -AND" diodes 12, 14 or the "OR" diodes 16 illustrated and in its operatiion may be made by those 
depending on the bias o n  the ,base of the output transis- skilled in the art, without departing from the spirit of the 
tors Q3 in elements 4 and 6. Since transistor Q2 in ele- 40 invention, it is intended that the invention <be limited 
merit 6 is conducting the output transistors 4 3  is in the only as indicated by the scope of the ~fofollowing claims. 
false (on) logic state ,(+0.9 volt), that is, transistor Q3's What is claimed is: 
base is so  biased that a positive pulse at  its emitter will I' In 
cause it to conduct (see waveform 4 3  ,hs, FIG. 3) .  ne fi"tl second, @ird, and fourth transistors each having 
clock pulse current will flow from ground 38 &rough the 45 a base* a and an emitter; 
collwtor of transistor Q3, its emit&-, output terminal 20 a first circuit means connecting the base of said first 
and then tlluough diode 14. In effect, an on transistor transistor with the collectw of said second transistor; 
Q3 will shunt .the clock pulse current away from the a second cirouit means for connecting the base of said 
"OR" diode. As a result the current will not be directed second transistor with the collector of said first 
to the "OR" circuit. 50 transistor; 
However, if the base of all transistors Q3 in elements a first delay network connecting the base of said third transistor to said first circuit means; 4 and 6 of the "AND" gate are biased so tihat they are a second delay network connecting base said in the "tmue" (off) logic state (+1.6 volts), the " A N D  fourth transistor to said second circuit means; diodes will be back biased with respect to  the voltage a means for applying recurring clock pulses to bhe 
across the "OR" diode. As a result the dock m r e n t  will 55 
then be directed to bhe input 22 of transistors Q1 and bases of said first and second transistors t o  vary the 
will provide a high positive bias on the base of transistor bias of said third and fourth transistors via come- 
Qf. This causes transistor Q1 to conduct and turns tran- sponding ones of said delay networks; and to the 
eistor 4 2  off. This also puts a high negative bias on pnp emitters of said third and fourth transistors to cause 
transislor QS. Transistor 43 is now conditioned to con- 60 conduction of one or the other thereof, as deter- 
duct when a ,positive clock pulse is applied to output mined by the bias applied thereto from said first and second transistors. 
terminal 20 of its emitter and is now in the "true" (on) 2. The as defined in claim svherein said 
state. will noted *hat amplifying transistors 4 3  first and second means each include a senies con- 
and Q4 are *lE until they are queried by a 65 nected unidirectional current conducting element. 
olock pdse. 3. The combination as defined in claim 1 wherein said 
The R c  delay nHwork comprising ssistor 34 136) and recurring clock pulses are applied through a &st cfSiode 
capacitor 2% (60) Prevents change of potential ihe connect& to the base of said filst transistor and a second 
base of transistor r C ? j  (Q4) during t h e  a @lmk diode connected to tile base of sail1 second tr;snsistor. 
i s  applied at  O u t P t  ~ i n t s  2@ f24)- ~~i~ Prevents a 70 4- The combination of a flip-At>p circuit comprising: 
second clock pulse, being applid at input terminal 22 a pair of fegeneralively cross-coupled switching transis- 
(26) from anobher logic circuit ohanging the stale of tars each having a base, an emitter, and a collector; 
transistor 43 (64) .  Otherwise there would be the pos- said emitters being connected in common and said 
sibility of transistor 43 (Q4) changing from a n  to off bases and collectors being cross-coupled; 
or vice versa d u r i a  the first clock pulse. 75 a source of operating potential; 
3,283,175 
5 
a source of bias potentila1 mnnectcd to said common- 
6 
a pair of 'diodes connected to t!x bases of wrmswnd- 
connected emitters; ing ones of said switching transistors; and said am- 
a pair of coupling networks connecting respective ones plifyirvg transistors connected to permit or prereent 
of said switahing transistors to said source of operat- applications of said clock pulse to said diodes to 
ing potential; 6 transfer the state of conduction of said switoh~ing 
a pair of amplifyiag transistors each having a base, transistors to control the bias of said anrflifyisig 
an emitter, and a collector: the collector of each of transistors. 
said amplifying transistors being connected to ground: 
a means connected to the emitters of said amplifying 
transistors and to the base of said switching transis- 
References Cited by &]he Emminer 
UNITED STATES PATEmS 
- 
tors for applying a recurring clock pulse thereto: 3,008,055 11/1961 Crosby et  al. -----.-- 307-88.5 
a pair of delay networks connecting the bases of w r -  
sespond'ing ones of said amplifying transistors to ARTHUR GAUSS, Examiner- 
corresponding ones of said coup~ngnetworks; 15 D. D. FORRER, Assistant Exarniaer. 


AC logic flip-flop circuits Patent

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