Digitally generated countdown pulse at submultiple frequency is applied to one electrode of FET gate to establish threshold state; gate cannot function until desired portion of reference half-wave pulse which is to be passed appears on second electrode

Lutes, G. F., Jr.

English

NASA Technical Reports Server

March 1973	 B73-10135 
•	 NASA TECH BRIEF 
NASA Pasadena Office 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage 
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Low Phase-Noise Digital Frequency Divider 
The problem: 
To minimize phase noise in the frequency-dividing 
circuits that are used in conjunction with atomic or 
maser frequency standards. 
Isolation	 Tuned	 Output 
Amplifier - - - -
	 Amplifier Amplifier 
Input	
I Gate 
 1 r-i
Digital 
Frequency 
Divider 
—1sinruir 
Phase 
Shifter •i 
The solution: 
A frequency dividing arrangement in which a digital 
divider and a gate are used in such a manner as to 
avoid the noise which characteristically occurs 
in other types of dividers. A digitally-gener-
ated countdown pulse at the submultiple frequency 
is applied to one electrode of an FET gate to establish 
a threshold state; the gate cannot function until the 
desired portion of the reference half-wave pulse which 
is to be passed appears on a second electrode. 
How it's done: 
As indicated in the diagram, a reference signal is 
introduced to the isolation amplifier and the amplified 
output is split; one portion is fed through a gate to a 
tuned amplifier, and the other portion is fed through
a voltage divider to a phase-shift network. 
The gate is essentially an FET transistor, Qi, 
operated as a switch. When the gate electrodes of Qi 
are biased negatively, no current can flow between its 
source and drain and the device acts as a high im-
pedance bypass on the output of the isolation ampli-
fier; thus, signals coming from the amplifier pass to 
the tuned amplifier and thence to a broadband output 
amplifier. On the other hand, when the FET gate 
electrodes are biased positively, current can flow be-
tween source and drain, and the device presents a 
very low impedance to the output of the isolation 
amplifier, effectively short circuiting the output to 
ground. 
The gate is controlled by an integrated circuit dig-
ital frequency divider set for any convenient division 
ratio which is a positive whole number. The fraction 
of the reference signal voltage coming from the phase 
shifter is amplified and then converted by a shaper 
into square waves of sufficient amplitude to drive the 
digital frequency divider module. 
The output of the digital divider is a positive-going 
square wave, but since a negative-going keying signal 
is needed for operation of the gate, the digital fre-
quency divider output is inverted by an amplifier at 
a voltage level sufficient to drive the FET gate tran-
sistor Qi. Ordinarily, noise from the digital divider 
and the gate appears in the vicinity of turn-on or 
turn-off. When gating is effected as shown in the dia- 
gram, noise cannot pass into the tuned amplifier be-
cause the keying pulse from the digital frequency 
divider is kept at a level which does not permit gate-
transistor Qi to open until the original reference sig-
nal positive half-wave crosses the zero axis in making 
(continued overleaf) 
	
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the transition from negative to positive. During the 
interval defined by the negative-going portion of the 
keying square wave and the crossing of the zero axis 
by the reference signal, Q1 remains in the conducting 
state, shorting the reference signal output from the 
isolation amplifier. The gate transistor goes into cutoff 
only when the negative-going keying pulse is present 
on the gate electrode and the positive-going portion 
of the reference signal appears on the drain; thus, 
transistor Qi is operated as an AND gate. 
It is apparent that in passing through the various 
branches of the frequency dividing circuitry, the orig-
inal signal will encounter different delays in. each 
branch. The phase shifter establishes the time rela-
tionship between the particular cycle of the reference 
signal whose positive half-wave portion becomes the 
divided-down signal and the keying pulse at Qi. A 
variable resistor in the phase-shifting network makes 
possible the proper coincidence of the reference sig-
nal and the keying signal. 
Notes: 
1. The gating arrangement is capable of operating 
satisfactorily at input frequencies up to 10 MHz.
2. Requests for further information may be directed 
to:
Technology Utilization Officer 
NASA Pasadena Office 
4800 Oak Grove Drive 
Pasadena, California 91103 
Reference: TSP 73-10135 
Patent status: 
This invention is owned by NASA, and a patent 
application has been filed. Inquiries concerning non-
exclusive or exclusive license for its commercial de-
velopment should be addressed to: 
NASA Patent Counsel 
Mail Code 1 
NASA Pasadena Office 
4800 Oak Grove Drive 
Pasadena, California 91103 
Source: George F. Lutes of 
Caltech/JPL
under contract to
NASA Pasadena Office 
(NPO-11569)
. 
1.jEl	 Category 01


Low phase-noise digital frequency divider

A low phase noise frequency divider composed of a grating arrangement is disclosed. The grating arrangement supplies selected portions of an input reference signal to be divided to a tuned circuit without any phase noise due to the grating action. The arrangement which in one embodiment consists of an FET is connected to the tuned circuit input to short out the input except when the input reference signal amplitude crosses ground level in a positive direction and a gate enabling signal is present at the gate electrode of the FET. The gate enabling signal alone does not decouple the tuned circuit input from ground, therefore phase noise, due to the leading and trailing edges of each gate-enabling signal, is substantially eliminated

Low phase-noise digital frequency divider

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