Speed required for Sisyphus experiment on Pioneer probe was attained at supply voltage well within component limitations by combining supply voltage higher than nominal with low reactance interconnections. Speed was found to be far in excess of typical. parameters suggested by manufacturers of MOS devices

Devlin, M.

English

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1972	 B72-10184 
NASA TECH BRIEF 
Ames Research Center 
NASA Tech Briefs announce new technology derived from the U.S. space program. They are issued to encourage 
commercial application. Tech Briefs are available on a subscription basis from the National Technical Information 
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be directed to the Technology Utilization Office, NASA, Code KT, Washington, D.C. 20546. 
Speed Enhancement of Complementary MOS Devices 
Space applications of solid-state digital circuits re-
quire low power dissipation and often are required 
to operate at high speeds. Frequently, high speed 
characteristics are sacrificed in order to limit power 
requirements - or power budgets are violated to en-
sure operation at desired speeds.
cuits is limited primarily by capacitive load, an inves-
tigation was made of the effects of combining a 
supply voltage higher than nominal with low react-
ance interconnections. It was found that speeds far 
in excess of the "typical" parameters suggested by 
manufacturers of MOS devices could be achieved, 
The "Sisyphus" experiment for a Pioneer probe 
required the operation of a binary counter at 4 MHz 
at low levels of power consumption, with bipolar 
TTL in the higher-speed portions of the circuits. 
Minimum weight requirements for the circuitry indi-
cated the necessity of high-density packaging. As 
a result of high-density packaging, the logical 
gain-bandwith product of the devices used was sig-
nificantly increased; this was attributed to short, 
low-capacity interconnections. 
Since complementary MOS devices operate at 
higher speeds as power supply voltages are increased, 
and the speed of operation of high-impedance cir-
and that the speed required for the space experiment 
could be attained at supply voltages well within com-
ponent limitations. 
The circuit shown in the diagram is typical for 
the high-speed applications required for the experi-
ment. It was tested for maximum speed of operation 
at room temperature for 22 samples of counter cir-
cuits, and at —45.6° and 65° C for two samples 
classed as "fastest" and "slowest". The tests were con-
ducted with loads simulating the proposed applica-
tion and with different values of supply voltage. 
(Flip-flop and gate samples were limited, but substi-
tution of one sample in each location produced only 
(continued overleaf) 
This document was prepared under the sponsorship of the National 
Aeronautics and Space Administration. Neither the United States 
Government nor any person acting on behalf of the United States
Government assumes any liability resulting from the use of the 
information contained in this document, or warrants that such use 
will be free from privately owned rights.
https://ntrs.nasa.gov/search.jsp?R=19720000184 2020-03-17T03:32:45+00:00Z
minor changes in maximum speed.) The signals were 
"normalized" by a flip-flop and traversed four stages 
before triggering the counter. 
The counter circuit used in the tests characteris-
tically operates at 2.5 MHz at 10 V; 6.16 MHz were 
attainable at a power supply of 8 V, and 8.96 MHz 
at 12 V when used in high density packages. 
Note: 
No additional documentation is available. Specific 
questions, however, may be directed to: 
Technology Utilization Officer 
Ames Research Center 
Moffett Field. California 94035 
Reference:. B72-10184
Patent status: 
No patent action is contemplated by NASA. 
Source: Michael Devlin of

General Electric Company,
Valley Forge Space Center

under contract to

Ames Research Center 
(ARC-10387) 
B72-10184	 Category 01


Speed enhancement of complementary MOS devices

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