Digital data handling circuits for pulse amplifier

Benedict, R. D.

English

NASA Technical Reports Server

NATIONAL AERONAUTICS AND SPACE ADMINISTRATION 
WASHINGTON, D.C. 20546 
REPLY TO 
ATTN OF: G P  June 30, 1971 
MEMORANDUM 
FROM : 
~ ~ ~ / s c i e n t i f i c  & Technical Information Division 
Attn: M i s s  Winnie M. Morgan 
G P / O ~  f i c e  of Assis tant  General 
Counsel f o r  Patent  Matters 
SUBJECT: Announcement of NASA-Owned U.S. Patents  i n  STAR 
I n  accordance with t h e  procedures contained i n  t he  Code G P  
t o  Code US1 memorandum on t h i s  subject ,  dated June 8, 1970, 
the  attached NASA-owned U.S. patent  i s  being forwarded f o r  
abs t rac t ing  and announcement i n  NASA STAR. 
The following information i s  provided: 
U.S. Patent  No. 
Corporate Source 
Supplementary 
Corporate Source 
: Radio Corporation of America 
NASA Patent  Case No.: XNP-01068 
Please note t h a t  t h i s  patent  covers an invention made by an 
employee of a NASA contractor .  Pursuant t o  $305(a) of t he  
NAS A c t ,  t h e  name of t he  Administrator of NASA appears on the  
f i r s t  page of t h e  patent ;  however, t he  name of the  actual 
inventor (author) appears a t  t he  heading of Column No. 1 of 
t h e  Specif ica t ion,  following the  words ". . . with respgckee- 
an invention of .  . . ." 
~ a ~ l e  Parker 
Enclosure : 
copy of Patent  
https://ntrs.nasa.gov/search.jsp?R=19710019263 2020-03-17T03:15:57+00:00Z
Sept. 6, 1966 JAMES E. WEBB 3,291,594 
ADMINISTRATOR ClF THE NATIONAL AERONAUTBCS 
AND SPACE ADM1NISTRATlON 
TRANSIENT AUGMENTATION CJKCUIT FOR PULSE AlfFLIF'IERS 
Filed June 16, 1964 
3,21 l,544 United States Patent Ofice ,,,, , ,,,, , 
1 2 
3,271,584 An important feature of the device of the invertiion i'.; 
TRANSIENT AUGkPENTA'FI8N c'dlWc&TIT ~~~ its simplicity and its relative Aexibiliiy i l i  s~:p;~i j~i :~~: 
PULSE ANIPLPIFBIERS various Ioad currents a t  a constant voitagz, mcrely by 
Ja:a~es E. ?Webb, Adminisbrrator of the Nationd Aem- selecting the proper shaping networks and l:ansislo:'s, 
mantics rand Space Admais~istra%ian wiih respect to an 
~ ~ n v ~ ~ l i o ~ a l  pulse amplifiers do not no r~~ ia l iy  sii~~irl- 
i~iiseaationn of Richard D. Benedict taneously supply a power pulse and maintain line volt- 
Piled June 16, 1964, Sea. No. 375,6868 age as is provided in the present invention. Convenlionai 
'7 Claims. (C1. 309-88.53 
circuits, used heretofore, have llormaliy reqtrii-eti adtli- 
This invention relates to digital data handling circuits tional circuits to provide clampi.e~g actior:. 
2nd more particularly to a pulse circuit which a~lgments Bt is therefore a principal object of ?he inveniieil 10 
the transient negative current capabilities of a pulse povqer lo provide novel alld improved pulse circrrit meens which 
amplifier. will provide or  augment the transient negaiivz ciirrcn! 
Frequeiltly the need arises in pulse transmission sys- capacities of a pulse amplifier. 
tenls for  amplifying a pulse signal with a minimunl of Another object of the invention is to provide ao~c ' r  
distortion. Also, it is important in the design of digital l5 and improved circuit nzeans for use in irnproviag ii:c 
logic to maximize high-speed capability. The problem high-speed capabilities of pulse power ar,ipiifiers. 
of minimizing transient distortioil in high-speed digital Yet another object of the invention is to providz ilov-1 
logic circuits has received the attention of many pulse and improved circuit means for minimizim~g pr;!se ciisi~i-  
circuit designers. While it is known that transient dis- tion in digital logic circuits. 
tortion and time degradation in p ~ ~ l s e  circuits can be 20 Still allother object of the invention is io  providi: nove? 
avoided or  cornpensaled in various ways, the way of and improved pulse circuit means for siippiying :he rc- 
doing so contemplated in the present invention has 'been quired load current in high-speed digital slJqitching cir- 
found to be pariicuIarly effective and economical. The cuits. 
useful applications of a circuit of this ~ a t u r e  are many, A general object of tlre invention is to proijick e 2 0 ~ ~ 1  
and will be readily apparent to those skilled in the art- 25 and illlproved pull-down circuit which overcon:es dis- 
The circuit of the presellt invention is especially use- advantages previous means and methods ker-eicforc 
fu l  in pulse amplification for digital logic circuits since intended to accompiisll generally pr!;.poses. it can supply the current required to discharge line Many oihcr .advantages, featr~rcs and additional objecls 
capacitances in a minialum of time, and at the same time of the present invention will becoille jn,anife~l those 
prevent distortion of the voltage pulse. A negative cur- 30 versed in the art upan making reference to lllc dclaiicd 
rent, as used hereinafter, is defined as flowing from the description and the accompanying of dra~vings 
load to the pulse ge13cralor. The application of the cir- which a preferxd siruclr!ral embodimc,r;T, ,jnccri30rnii;lg 
cuit of ttre inventio~i is primarily directed to those cases the principles of the present invention is shown by ivny of 
En which the load may be reduced to an equivalent series illustrative 
RLC circuit which is over damped. Negative current 25 ]in the drawings: 
drive is required for such a load for two j?ossible reasons. FIGURE. 1 is a schen~alic ircuit diagram of a proferr-cd 
One reason is to discharge the load capacitance in a rela- of the invenbion. 
tively short period of time. The second reason is t o  FIGURE 2 is a waveform diagram of ~ssista:ice in thz 
"pull down" or  "110ld down" the load input voltage to exposition of the invention, 
its negative level during the time the Ioad capacitance i s  4 0  Broadly, the concept relakes to a circi.iii b-viiig two ;;I- 
discharging. These functions are provided by the novel vertcr stages and a positive feedback pat11 bztwecn t ! ~  two 
circuit of the present invention. A feaklre of the circuit iilverters, the circuit being arranged to pull <:own, or 
of the invention is that it is short circuit safe; i.e., the down, the input voltage to its ne,oative IevcE drlriag h:re 
output may be short circuited to ground potential for  an  discharge interval of the load capacitance. 
indefinite period of time wiihonh damaging the circuit. Looking now at FIGURE I there is s11owa a sc~~ernatic 
Stated diBerentI~1, the apparatus of the present inven- 4'5 diagram of a preferred embodinlent ,;f ille E ~ ~ v c ~ ~ ; i o ~ .  
tion comprises a feedback ailzplifier capable of supplying Terminal 1 comprises a common input-or~tput conncciion 
negative current to over damped series W.E circuits. to the circuit and is connected to the pulse ampiifi-r 33 
A typical ernbodinlent conlprises a two-stage transistor by line 35. The circuit is designed 13 opcrztc wii!l 
inverter, which supplies base drive to the second stage loads which .are the equivalent of an  overda3rp.d series 
amplifier through an over damped series RLC coupling 50 RE&I circuit, as &own generally at  31, $11~ acii-ge ci:.- 
network. The collector for  the second stage anrplifier is cuit elenaents comprise transistors 2 ancs 3 wl~ich ;ire ;rr- 
connected lo the input of the first stage amplifier, pro- ranged in a cascaded two-stage inverter amplifier. circuit 
viding rzgeneralion. The emitter of 'the second amplifier positive feedback aroiind both stages. signal 
stage is clamped to the reference logic level such that applied to terminal 1 ,is supplied to the base of PNp t1.a~~- 
the input voltage is maintained during the pulse. 55 sistor 3 via diode 4 and series resistor 5. Resistor 5 is 
The "short-circuit safe" feature of the invenlian arises shun:& by capacitor 6. A positive &iyernti!lg pc:enii,ii 
from its design which permits the input-output terminal is supplied to the input stage (3) via resjs;,or '7 crici P3wer 
to be shorted to ground potential. This condition places supply terminal 8. This positive supp,ky is nomillaliy +26 
the circuit in !he "off" slatc. during which both transistors volts in a typical construction of the The emitlei. 
are cut 0fE. AS the transistors are essentially open cir- of tralsistor 3 is returned to ground 9. T ! ~ ~  c o i ~ c t ~ ~ 0 7  of 
cuits when cut off, the circuit does not dissipate power transistor 3 is referellced to a negative supply vclrage 
except when supislying a load. This capability improves (nominally -26 volts) via resistor 11 and t e r i ~ i ~ i a l  12. 
the efficiency of the circuit and also precludes the pos- The collector is clamped at a negative I~cveE by iilenss 
sibility of damage if the output is inadvertently shorted. diode 24. Nominally, the clamp level is si:t at -65 
The circuit of the invention is also useful for restoring which is supplied via tcrnlinai 25. 
degraded pulse data at  the same time it speeds digital Base drive to the second stage inverter ~ ~ i ~ p i i f i ~ i .  ( 2 )  i s  
switching time by s~~pplying the required load currents. supplied through a critically darnpsd scrie:; RLC ca!?;iiig 
The circuit is applicable lo a variety of pulse handling network. This coupling network comprises ii.!duci,nnce ZIP, 
systems such as industrial process controllers, computers, 70 series resistor 15, and capacitors 16 and IT IBBdLic!nncc 
and telemetry systems as well as in space craft instna- 14 is shunted by diode 22. The series ~ o ~ ~ b i ~ ~ ~ t i ~ ~  ii;- 
mentation. ductance 14 and resistor 15 is shunted b,y diode 23. The 
3,271,594 
3 4 
i r JL t z f  i~:c R P C  network (14-17, 22 and 2 3 )  drives the input-ovlput teilninal means joining the input of said 
hili5 oi NPNr i-ans~stor 2. The emitter of transistor 2 is first inverter amplifier and output of said second 
c rect y c j l r c c  i.d to the negative clamp voltage supply inverter ampl~fi-r to provide regeneration in s a d  
(rzom r,illy -6 5 )  via terminal 26, and is clamped to  the tl'rnsient augmentatioil circuit. 
rc cr,-.ice hgic lcvel such that the input voltage is main- 5 2 An apparatus as defined in claim 1 in which said 
i l l  12d diiring tile pulse. The base of transistor 2 obtains second inverter ampilfier includes: voltage clamp means 
I s cutoff 03,s I-.; ientlal v ~ a  resistor 89. The collector of for 
t r  n51sio~ 2 is rcturned directly to the input-output ter- maintaining a gigen negative input voltage level at 
n a Tf the iicitage level at inp~:t-output terminal 1 said input-output tcrminal means during a current 
goca to gmiind potential (9)  when transistor 2 1s ON, 10 change at said input-output terminal. 
t-cinsiiic i 3 is cr t oR and t r a n s ~ ~ t o r  2 is cut off by reverse 3. An apparatus as defined in c l a m  1 whciein said 
b?\e i i  1ve r ~ ~ o i ~ g h  capacitors 15 and 17, diode 23, and netwo~lc comprises: 
i - s i~ io~s  I1 and 13. Thus, the pull-down circuit is short an  inductarlce, a resistance, and a capacitance, con- 
L I ~ :  &i4 s;ft Tranblstoi 2,  whlch provides a low impedance nccled ~n series; ancl 
p.'.h Fo the negative transient load current, is cut off 15 a first diode shunt-connected acloss said ;ndL:ctancc, 
-iirdci O C vo l t~pe  conditions at the input-output termi- and 
I I ~  i a second drode shunt-coilnected across the se~ies  corn- 
VIiwel t1.e voltage at the input-output terminal 1 falls b~nation of said inductance and s a d  rcslslance 
lrorn gro~ini: (9) to -6.5, transistor 3 is saturated. Tran- 4. An  appa~atus  as defined in claim B wherein said 
s , lo r  3 gxeiztes  base current to  saturate transistor 2. 20 first tnverter amplifier comprises: 
rrnnslstoj 2 also acts as a voltage inverter. The positive a PNP transistor amplifier; and said second inverter 
1:edba~ic 22th from the collector of transislor 2 to the ampkfier compiises an NPN transistor ainphfier. 
111 1:-c~tpiit teirqlqal I, together with the characteristical- 5 .  A transient augmentallon c~rcuit  comprlslng: 
iy  bi_:i. loop zaln of the two arnpllfier stages makes the an ~nput-output termlnal for connect~ng said pulse cir- 
L O I I ~ ~ I ~ ~ J S ~  i e ~ e n e r ~ ~ t ~ v e .  That is to say, that once the volt- 25 cult to an external transient augmentatton carrying 
age . e ~ c l  . t  !he mput-output terminal 1 drops, the pull- llne and to  a load having an equivalent overdamped 
down L I V L I L ~  EOICCS the voltage to stay at the lower level senes resistance-inductance-capacitance crrcu~i; 
loi LL pe ~ o d  OL time, provided that the load cnrrrent sup- a first transistor havleg a base, a grounded em~tter,  and 
pl 261 to irie coilector of transistor 2 is not large enough a collcctor; 
L ) iorcc I r 'insist01 2 out of saturation. 30 a source of negative opelating potentral connected to 
111, ki C b,~se neiworh d r ~ v ~ n g  transistor 2 generates the collector of said first transcsto-; 
cj sasz ciir l en t  vel sus time waveform which has the same a first nctwork connect~ng ihe base of said first tran- 
s 1 ipe di !be n,gative short circuit current of an over- s~stor  to said input-output ierminal; 
iixnpetl RLC c ~ r c u ~ t  load. There is shown in FIGURE a source of positive operating potential ccnnected to  
t a ~ypicdl negative short circuit current waveform, in 35 the junction between said first network and base of 
~ ~ h i c b  a11 pl t u d ~  LS plotted as a function of time, of an said first transistor: 
overdamped KC' load. As can be seen, the current a second trans~stor having a base, an emiiter, and a 
,r:.p:i tide iises s~mewha t  sharply to a peak value and collector, and having compleinentary symmetry wlth 
t '>c r , a l~~r  g, ,~Ji~ally decreases. The RLG base network of respect lo said first transistor; 
trzniiltor Z generates a base current versus time wave- 40 an overdamped series res~stance indllciance-capacitance 
7 0  PI i iesponie to a step change at the input-output network connected between the collector of said 
I-inn-1'1 , which is essentially the same shape as the nega- first trans~stor and the bdse of s a d  second tlansistor, 
hi\ e sbolt c ;ciui ~ i l i en t  wavefannl shown in FIGURE 2. a source of negative bias potential connected to thc 
-he proJ,lct ot the base current of transistor 2 and the emitter of said second transistor; and 
~Lilrcn?. giun of this transistor proctuces a permissible col- means connecting the col?ector of said second tmn- 
l i i ~ l ~ r  cd seqt uaveform on L:ne 2i 'which is sufficiently q.j sistor to  said inpot-output terminal to piovide re- 
: L I  L c f r j ;  Ihe negatkve short c~rcult  current wave- gene1 ation in said translent augmentation circnit and 
.arm o' .n overclamped RLC circuit load connected to to marntain said input-output terminal rncans at a 
I I 60th transistors ( 2  and 3) are essent~ally predetermined negative voltage level d ~ ~ i n g  a cur- 
o - ~ m  c~11cl i b  v bcin cut OR and do not d~ssipate power ex- rent change a t  said input-output terniiaal. 
 LA,^ uit-n slipplying a load. This feature improves the 50 6. An apparatus as defined in claim 5 including: 
d L i ~ ~ ~ ~ ~  i f f  L I a x j i  and precludes damage if the input is in- clamp means connected between the collector of said 
,idvcr~cnt'y ~horicd. first transistor and said source of negative blas 
VVfilic there haxqe been shown and described and pointed potenlial. 
oi t :lie i?diinlenial novel featules of the invention as ap- 7. An apparatus as defined in claiin 5 including: 
I Leu lo a preiericd embodinlent, it will be understood g j  clamp means connected between the base of said sec- 
ih'it V I L I L L I ~  01 ISSIOCIS and substitutions and changes in ond transistor and said source of negatibe bizs 
'hc Poiin ~ s r d  det-ills of the device illustrated and in its potential. 
c n n a ~ r d n  mc1y be made by those skilled in the art, without 
c i e p a ~ ~ , r  i. tram the s ~ m t  of the invention; therefore, ~t References C t e d  by the Emminer 
3s ~ n i e r i : ~  [hat the iniention be limited only as indicated 60 
oy thc sco,?e 3C i jic following claims: 
Wbni 13 c'anlned IS: 
B /"i lrdl-bLefil augmentation circuit for a pulse an-npli- 
Sizr hall( g nn equivalent overdamped serics resistance- 
id~~~t,i17~e-c~1pil~*:a11ce load omprising: 65 
a fx-21 imerlcr ai~lpilfier having an input and output; 
a s e ~ o n d  17verter amplifier having an input and output; 
STATES PATENTS 
Wright ------------ 307-85.5 
Bianchi ----------- 307-88.5 
Cleland ----------- 307-88.5 
Nichols ----------- 307-88.5 
Fischman et al. ----- 307-88.5 
Baron et al. 
<L res s,ance-I ~ductance-capacitance network connected Weferenses Cited by the hpplienat 
;idt?iiiel> the o~ilput of said first inverter amplifier 
2r13 inp.,t ci' said second amplifier, the current ampll- 70 
UNITED STATES PATENTS 
L L  ce  iiclsrrs time characteristic of said network, in 2,961~552 G. J. C. Andresen. 
rcspo lse to 1 step change input, being proportional 3 j 0 8 3 j 3 0 3  W. S. Pcnowles et 31. 
-o the ncgative short circuit current versus t ~ m e  
cilaa 1ctcr;stic of an overdamped series resistance- GAUSS. Pri'na'y 
,i dsr~tance-~apacitance load; and 75 I. C .  EDELL, Assistant Excmlltzer. 


Transient augmentation circuit for pulse amplifiers Patent

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